M15F2G16128A-BDBG2F - 16M x 16 Bit x 8 Banks DDR III SDRAM

ESMT

Description

The 2Gb Double-Data-Rate-3 (DDR3) DRAM is double data rate architecture to achieve high-speed operation.

It is internally configured as an eight bank DRAMs.

The 2Gb chip is organized as 16Mbit x 16 I/Os x 8 bank devices.

and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK 　falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous fashion. These devices operate with a single 1.5V ± 0.075V power supply and are available in BGA packages. Elite Semiconductor Memory Technology Inc Publication Date : Jul. 2013 Revision : 1.0.

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ESMT DDR III SDRAM Feature z 1.5V ± 0.

Published: Apr 18, 2019 |