M14D5121632A-1.8BG2A Datasheet

Features and Benefits

 JEDEC Standard
 VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V
 Internal pipelined double-data-rate architecture; two data access per clock cycle
 Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation.
 On-chip DLL
 Differential clock inputs (C.