logo

M14D5121632A-1.8BG2A Datasheet

Download Datasheet
ESMT · M14D5121632A-1.8BG2A File Size : 2.04MB · 4 hits

Features and Benefits


 JEDEC Standard
 VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V
 Internal pipelined double-data-rate architecture; two data access per clock cycle
 Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation.
 On-chip DLL
 Differential clock inputs (C.

M14D5121632A-1.8BG2A M14D5121632A-1.8BG2A M14D5121632A-1.8BG2A
TAGS
DDR-II
SDRAM
M14D5121632A-1.8BG2A
M14D5121632A-1.8BG2M
M14D5121632A-1.8BBG2A
Stock and Price
Since 2006. D4U Semicon.   |   Contact Us   |   Privacy Policy