M13S64164A-6BG sdram equivalent, 1m x 16 bit x 4 banks double data rate sdram.
z JEDEC Standard z Internal pipelined double-data-rate architecture, two data access per clock cycle z Bi-directional data strobe (DQS) z On-chip DLL z Differential clock.
Image gallery
TAGS
Manufacturer
Download (1.51MB)