M13S64164A-5BG
Key Features
- z JEDEC Standard
- Internal pipelined double-data-rate architecture, two data access per clock cycle
- Bi-directional data strobe (DQS)
- Differential clock inputs (CLK and CLK )
- DLL aligns DQ and DQS transition with CLK transition
- Quad bank operation
- Burst Type : Sequential and Interleave
- All inputs except data & DM are sampled at the rising edge of the system clock(CLK)
- Data I/O transitions on both edges of data strobe (DQS)
- DQS is edge-aligned with data for reads; center-aligned with data for WRITE
