Datasheet4U Logo Datasheet4U.com

M12L64322A-7BG2S - 512K x 32 Bit x 4 Banks Synchronous DRAM

Download the M12L64322A-7BG2S datasheet PDF. This datasheet also covers the M12L64322A variant, as both devices belong to the same 512k x 32 bit x 4 banks synchronous dram family and are provided as variant models within a single manufacturer datasheet.

Description

The M12L64322A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits.

Features

  • JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency ( 2 & 3 ) - Burst Length ( 1, 2, 4, 8 & full page ) - Burst Type ( Sequential & Interleave ) All inputs are sampled at the positive going edge of the system clock Burst Read Single-bit Write operation DQM for masking Auto & self refresh 64ms refresh period (4K cycle) M12L64322A (2S) 512K x 32 Bit x 4 Banks Synchronous DRAM.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (M12L64322A-ESMT.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number M12L64322A-7BG2S
Manufacturer ESMT
File Size 815.28 KB
Description 512K x 32 Bit x 4 Banks Synchronous DRAM
Datasheet download datasheet M12L64322A-7BG2S Datasheet

Full PDF Text Transcription

Click to expand full text
ESMT SDRAM FEATURES JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency ( 2 & 3 ) - Burst Length ( 1, 2, 4, 8 & full page ) - Burst Type ( Sequential & Interleave ) All inputs are sampled at the positive going edge of the system clock Burst Read Single-bit Write operation DQM for masking Auto & self refresh 64ms refresh period (4K cycle) M12L64322A (2S) 512K x 32 Bit x 4 Banks Synchronous DRAM ORDERING INFORMATION Product ID Max Freq.
Published: |