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M12L32162A-7TG - 1M x 16Bit x 2Banks Synchronous DRAM

Download the M12L32162A-7TG datasheet PDF. This datasheet also covers the M12L32162A variant, as both devices belong to the same 1m x 16bit x 2banks synchronous dram family and are provided as variant models within a single manufacturer datasheet.

Description

The M12L32162A is 33,554,432 bits synchronous high data rate Dynamic RAM organized as 2 x 1,048,576

Features

  • z JEDEC standard 3.3V power supply z LVTTL compatible with multiplexed address z Dual banks operation z MRS cycle with address key programs - CAS Latency (2 & 3 ) www. DataSheet4U-. comBurst Length (1, 2, 4, 8 & full page) - Burst Type (Sequential & Interleave) z All inputs are sampled at the positive going edge of the system clock z Burst Read Single-bit Write operation z DQM for masking z Auto & self refresh z 64ms refresh period (4K cycle).

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (M12L32162A_EliteSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number M12L32162A-7TG
Manufacturer ESMT
File Size 755.29 KB
Description 1M x 16Bit x 2Banks Synchronous DRAM
Datasheet download datasheet M12L32162A-7TG Datasheet

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Other Datasheets by ESMT

Part Number Description
M12L32162A-7BG 1M x 16Bit x 2Banks Synchronous DRAM
M12L32321A-5BG2G 512K x 32Bit x 2Banks Synchronous DRAM
M12L32321A-6BG2G 512K x 32Bit x 2Banks Synchronous DRAM
M12L32321A-7BG2G 512K x 32Bit x 2Banks Synchronous DRAM
M12L128168A-5BG 2M x 16 Bit x 4 Banks Synchronous DRAM

Full PDF Text Transcription

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ESMT Preliminary Revision History Revision 0.1 (Aug. 11 2006) - Original Revision 0.2 (Mar. 20 2007) - Add BGA package Revision 0.3 (Apr. 27 2007) - Rename BGA pin name (BA1 to NC; BA0 to BA) - Modify DC Characteristics www.DataSheet4U.com M12L32162A Elite Semiconductor Memory Technology Inc. Publication Date : Apr. 2007 Revision : 0.3 1/29 ESMT SDRAM Preliminary M12L32162A 1M x 16Bit x 2Banks Synchronous DRAM FEATURES z JEDEC standard 3.3V power supply z LVTTL compatible with multiplexed address z Dual banks operation z MRS cycle with address key programs - CAS Latency (2 & 3 ) www.DataSheet4U-.
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