M12L128168A-7TVAG2S dram equivalent, 2m x 16 bit x 4 banks synchronous dram.
* JEDEC standard 3.3V power supply
* LVTTL compatible with multiplexed address
* Four banks operation
* MRS cycle with address key programs
- CAS Latency .
The M12L128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. R.
Image gallery
TAGS
Download (Size : 1.02MB)