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M12L128168A-6TG2S - 2M x 16 Bit x 4 Banks Synchronous DRAM

Download the M12L128168A-6TG2S datasheet PDF. This datasheet also covers the M12L128168A variant, as both devices belong to the same 2m x 16 bit x 4 banks synchronous dram family and are provided as variant models within a single manufacturer datasheet.

Description

The M12L128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits.

Features

  • JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency ( 2 & 3 ) - Burst Length ( 1, 2, 4, 8 & full page ) - Burst Type ( Sequential & Interleave ) All inputs are sampled at the positive going edge of the system clock Burst Read single write operation DQM for masking Auto & self refresh 64ms refresh period (4K cycle) M12L128168A (2S) 2M x 16 Bit x 4 Banks Synchronous DRAM.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (M12L128168A_EliteSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number M12L128168A-6TG2S
Manufacturer ESMT
File Size 785.62 KB
Description 2M x 16 Bit x 4 Banks Synchronous DRAM
Datasheet download datasheet M12L128168A-6TG2S Datasheet

Full PDF Text Transcription

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ESMT SDRAM FEATURES JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency ( 2 & 3 ) - Burst Length ( 1, 2, 4, 8 & full page ) - Burst Type ( Sequential & Interleave ) All inputs are sampled at the positive going edge of the system clock Burst Read single write operation DQM for masking Auto & self refresh 64ms refresh period (4K cycle) M12L128168A (2S) 2M x 16 Bit x 4 Banks Synchronous DRAM ORDERING INFORMATION Product ID M12L128168A-5TG2S M12L128168A-5BG2S M12L128168A-6TG2S M12L128168A-6BG2S M12L128168A-7TG2S M12L128168A-7BG2S Max Freq.
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