F50D2G41LB-66YG2M
Key Features
- Voltage Supply: 1.8V (1.7V~1.95V)
- Organization - Memory Cell Array: (128M + 4M) x 8bit - Data Register: (2K + 64) x 8bit
- Automatic Program and Erase - Page Program: (2K + 64) Byte - Block Erase: (128K + 4K) Byte
- Page Read Operation - Page Size: (2K + 64) Byte - Read from Cell to Register with Internal ECC: 100us
- Memory Cell: 1bit/Memory Cell
- Support SPI-Mode 0 and SPI-Mode 31
- Fast Write Cycle Time - Program time:400us - Block Erase time: 4ms
- Hardware Data Protection - Program/Erase Lockout During Power Transitions
- Reliable CMOS Floating Gate Technology - Internal ECC Requirement: 1bit/512Byte - End
