74LVC240A Datasheet | Diodes Incorporated

Description The 74LVC240A provides two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. The device is designed for operation with a power supply range of 1.65V to 3.6V. The inputs are tolerant to 5.5V allowing this device to be used in a mixed voltage environment. The device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output preventing damaging current backflow when the device is powered down. Features - Supply Voltage Range from 1.65V to 3.6V - Sinks or Sources 24 ma at VCC = 3V - CMOS Low Power Consumption - IOFF Supports Partial -Power Down Operation - Inputs or Outputs Accept up to 5.5V - Inputs Can Be Driven by 3.3V or 5V Allowing for Mixed Voltage Applications - Schmitt Trigger Action at All Inputs - Typical VOLP (Quiet Output Ground Bounce) Less than 0.8V with VCC = 3.3V and TA = +25°C - Typical VOHV (Quiet Output dynamic VOH) Greater than 2.0V with VCC = 3.3V and TA = +25°C - ESD Protection Tested per JESD 22 - Exceeds 200-V Machine Model (A115) - Exceeds 2000-V Human Body Model (A114) - Exceeds 1000-V Charged Device Model (C101) - Latch-Up Exceeds 250m A per JESD 78, Class I - All devices are: - Totally Lead-Free & Fully Ro HS pliant (Notes 1 & 2) - Halogen and Antimony Free.“Green” Device (Note 3) Pin Assignments 1OE 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND ( Top View ) 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 TSSOP-20 Vcc 2OE 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 ( Top Transparent View) terminal 1 index area 1 1OE 20 Vcc 1A1 2 2Y4 3 1A2 4 2Y3 5 1A3 6 2Y2 7 1A4 8 2Y1 9 19 2OE 18 1Y1 17 2A4 16 1Y2 15 2A3 14 1Y3 13 2A2 12 1Y4 GND 10 2A1 11 QFN-20 Applications - General Purpose Logic - Bus...