74AUP2G02
Description
Pin Assignments The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP2G02 is a dual two-input NOR gate.
Key Features
- Advanced Ultra Low Power (AUP) CMOS
- Supply Voltage Range from 0.8V to 3.6V
- ±4mA Output Drive at 3.0V
- Low Static Power Consumption ICC < 0.9µA
- Low Dynamic Power Consumption CPD = 6 pF (Typical at 3.6V)
- Schmitt Trigger Action at all inputs makes the circuit tolerant for slower input rise and fall time. The hysteresis is typically 25
