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Deutron Electronics

P3R1GE3JGF Datasheet Preview

P3R1GE3JGF Datasheet

1G bits DDR2 SDRAM

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DATA SHEET
1G bits DDR2 SDRAM
P3R1GE3JGF(128M words × 8 bits)
P3R1GE4JGF(64M words × 16 bits)
Specifications
Density: 1G bits
Organization
16M words × 8 bits × 8 banks (P3R1GE3JGF)
8M words × 16 bits × 8 banks (P3R1GE4JGF)
Package
60-ball FBGA (P3R1GE3JGF)
84-ball FBGA (P3R1GE4JGF)
Lead-free (RoHS compliant) and Halogen-free
Power supply: VDD, VDDQ = 1.8V ± 0.1V
Data rate
800Mbps (max.)
1KB page size (P3R1GE3JGF)
Row address: A0 to A13
Column address: A0 to A9
2KB page size (P3R1GE4JGF)
Row address: A0 to A12
Column address: A0 to A9
Eight internal banks for concurrent operation
Interface: SSTL_18
Burst lengths (BL): 4, 8
Burst type (BT):
Sequential (4, 8)
Interleave (4, 8)
/CAS Latency (CL): 3, 4, 5, 6
Precharge: auto precharge option for each burst
access
Driver strength: normal, weak
Refresh: auto-refresh, self-refresh
Refresh cycles: 8192 cycles/64ms
Average refresh period
7.8µs at 0°C TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
Operating case temperature range
TC = 0°C to +95°C
Features
Double-data-rate architecture; two data transfers per
clock cycle
The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
Data mask (DM) for write data
Posted /CAS by programmable additive latency for
better command and data bus efficiency
Programmable RDQS, /RDQS output for making × 8
organization compatible to × 4 organization
/DQS, (/RDQS) can be disabled for single-ended
Data Strobe operation
Off-Chip Driver (OCD) impedance adjustment is not
supported.
Datasheet V2.1 Deutron Electronics Corp.




Deutron Electronics

P3R1GE3JGF Datasheet Preview

P3R1GE3JGF Datasheet

1G bits DDR2 SDRAM

No Preview Available !

D
Ordering Information
Part number
Die
revision
P3R1GE3JGF-G8E
J
P3R1GE4JGF-G
Organization
(words × bits)
128M x 8
64M × 16
Part Number
P3R1GE3JGF, P3R1GE4JGF
Internal
banks
8
Speed bin
(CL-tRCD-tRP)
DDR2-800 (5-5-5)
DDR2-800 (5-5-5)
Packag
60-ball FBGA
84-ball FBGA
Device Body
Speed
P 3 R 1G E
1 2 3 4,5 6
3J GF - G
7 8 9 10 11 12
8E U
13 14
14. eTT Grade
13. Speed 8E: DDR2-800
12. Green
10. Package Type F:FBGA
9. Process Generation
8. Die Rev.
7. Organization 3:x8,4:x16
6. Synchronous DRAM
4,5.Density
3. Interface
R:1.8V SSTL_18
2. Memory Style (DRAM)
1. Mira DRAM
2009/7/15
.
2


Part Number P3R1GE3JGF
Description 1G bits DDR2 SDRAM
Maker Deutron Electronics
Total Page 30 Pages
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