ADC305 Datasheet | Datel

® ® ADC-305 8-Bit, 20MHz CMOS A/D Converters Features - - - - - - - 8-bit resolution, 20MHz min. sampling rate ±½LSB max. differential nonlinearity error 18MHz input signal bandwidth Subranging, S&H enclosed +5V single power, low 85m W max. dissipation CMOS patible logic input 3-State TTL patible output GENERAL DESCRIPTION DATEL's ADC-305 is an 8-bit, 20MHz sampling, CMOS, subranging (two-pass) A/D converter. It processes signals at speeds parable to a full flash converter by using a subranging conversion technique with multiple parator blocks, each containing a sample and hold amplifier. The ADC-305 Features CMOS low power dissipation (60m W typical) and a wide 18MHz (- 1d B) input signal bandwidth. The ADC-305-1 is packaged in 400 mil 24-pin DIP and the ADC-305-3 in 300 mil 24-pin SOP. Other Features are CMOS patible input logic, 3-state TTL patible output logic, +5V single power operation, self bias mode and low cost. PIN 1 2 3 4 5 6 7 8 9 10 11 12 INPUT/OUTPUT CONNECTIONS FUNCTION OUTPUT ENABLE (OE) DGND BIT 8 (LSB) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 (MSB) +DVS (+5V) CLOCK INPUT (A/D CLK) PIN 24 23 22 21 20 19 18 17 16 15 14 13 FUNCTION DGND REF. BOTTOM (VRB) SELF BIAS 1 (VRBS) AGND AGND ANALOG INPUT (VIN) +AVS (+5V) REFERENCE TOP (VRT) SELF BIAS 2 (VRTS) +AVS (+5V) +AVS (+5V) +DVS (+5V) Both the ADC-305-1 and the ADC-305-3 have the same pin assignment. OUTPUT ENABLE 1 DGND 2 BIT 8 (LSB) 3 BIT 7 4 BIT 6 5 BIT 5 6 BIT 4 7 BIT 3 8 BIT 2 9 BIT 1 (MSB) 10 +DVS 11 A/D CLK 12 CLOCK GENERATOR UPPER DATA LATCHES LOWER ENCODER (4 BIT) A BLOCK PARATORS WITH S/H (4 BIT) LOWER DATA LATCHES LOWER ENCODER (4 BIT) B BLOCK PARATORS WITH S/H (4 BIT) REFERENCE VOLTAGE 24 DGND 23 VRB 22 VRBS 21 AGND 20 AGND 19 VIN 18 +AVS 17 VRT UPPER ENCODER (4 BIT) UPPER PARATORS WITH S/H (4 BIT) 16 VRTS 15 +AVS 14 +AVS 13 +DVS Figure 1. Functional Block Diagram DATEL, Inc., Mansfield, MA 02048-1151 (USA) - Tel: (508)339-3000, (800)233-2765 Fax:...