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W162 - Spread Aware/ Zero Delay Buffer

General Description

Reference Input: The output signals QA0:3 through QB0:3 will be synchronized to this signal unless the device is programmed to bypass the PLL.

Feedback Output: This signal is used as the feedback internally to establish the propagation delay of nearly 0.

Key Features

  • Spread Aware™.
  • designed to work with SSFTG reference signals.
  • Two banks of four outputs, plus the fed back output.
  • Outputs may be three-stated.
  • Available in 16-pin SOIC or SSOP package.
  • Extra strength output drive available (-19 version).
  • Internal feedback Table 1. Input Logic SEL1 0 0 1 1 SEL0 0 1 0 1 QA0:3 ThreeState Active Active Active QB0:3 ThreeState ThreeState Active Active PLL Shutdown Active, Utilized Shutdown, Bypassed Activ.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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W162 Spread Aware™, Zero Delay Buffer Features • Spread Aware™—designed to work with SSFTG reference signals • Two banks of four outputs, plus the fed back output • Outputs may be three-stated • Available in 16-pin SOIC or SSOP package • Extra strength output drive available (-19 version) • Internal feedback Table 1. Input Logic SEL1 0 0 1 1 SEL0 0 1 0 1 QA0:3 ThreeState Active Active Active QB0:3 ThreeState ThreeState Active Active PLL Shutdown Active, Utilized Shutdown, Bypassed Active, Utilized QFB Active Active Active Active Key Specifications Operating Voltage: ............................................... 3.3V±10% Operating Range: .................................15 < fOUT < 133 MHz Cycle-to-Cycle Jitter: ..................................................