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SG556 Datasheet

Mobile Pentium Processor Application Clock Generator

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APPROVED PRODUCT
SG556
Mobile Pentium® Processor Application Clock Generator
with SSCG, USB and Power Management Support
Product Features
n Supports clock requirements for Mobile Pentium®
Processor
n 2 Host and 5 PCI clocks
n Separate supply pins for mixed (3.3/2.5V) voltage
application.
n <175ps skew among CPU clocks.
n < 250ps skew among PCI clocks.
n 48mhz for USB.
n 28-pin SSOP package for minimum board space.
n Power management capabilities
Frequency Table
SEL100/66#
CPU
PCI
0
66.4 Mhz*
33.3 Mhz
1
99.8 Mhz**
33.2 MHz
*Down Spread 1.25% (total); **Down Spread .5% (total)
Block Diagram
XIN
XOUT
OSC
CPU_STOP#
PCI_STOP#
SEL1066#
PWR_DWN#
PLL
PLL
VDDR
REF
VDDC
CPUCLK (0:1)
VDDP
PCI (1:5)
PCI_F
48 MHz
Pin Configuration
XIN
XOUT
VSS
PCI_F
PCI1
VDDP
PCI2
PCI3
VDDP
PCI4
PCI5
VSS
VDD
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VSS
27 VDDR
26 REF
25 VDDC
24 CPU0
23 CPU1
22 VSS
21 VDD
20 VSS
19 PCI_STOP#
18 CPU_STOP#
17 PWR_DWN#
16 48M
15 SEL100/66#
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07016 Rev. **
5/17/2001
Page 1 of 10


Cypress Semiconductor Electronic Components Datasheet

SG556 Datasheet

Mobile Pentium Processor Application Clock Generator

No Preview Available !

APPROVED PRODUCT
SG556
Mobile Pentium® Processor Application Clock Generator
with SSCG, USB and Power Management Support
Pin Description
PIN No. Pin Name PWR I/O TYPE
Description
1
XIN
VDD
I OSC1 On-chip reference oscillator input pin. Requires either an
external parallel resonant crystal (nominally 14.318 MHz) or
externally generated reference signal
2
XOUT
VDD O OSC1 On-chip reference oscillator output pin. Drives an external
parallel resonant crystal. When an externally generated
reference signal is used at Xin, this pin is left unconnected
15 SEL100/66# -
I PADI4 Frequency select input pins. See frequency select table on
page 1.
23, 24
CPUCLK VDDC O BUF1 Clock outputs. CPU frequency table specified on page 1.
(0:1)
4
PCI_F
VDDP O BUF4 Free running PCI clock. When PCI_STP# = 0, this clock does
NOT stop.
16 48M VDD48 O BUF3 48 MHz fixed clock.
5, 7, 8,
10, 11
PCI(1:5) VDDP O BUF4 PCI bus clocks. See frequency select table on page 1.
26
REF
VDDR O BUF3 Buffered outputs of on-chip reference oscillator.
19 PCI_STOP# -
I PAD When driven to a logic low level, this pin will synchronously stop
PU all PCI clocks (except PCI_F) at a logic low level.
18 CPU_STOP# -
I PAD When driven to a logic low level, this pin will synchronously stop
PU all CPU clocks at a logic low level.
17 PWR_DWN# -
I PAD This pin is active low. When asserted low, the device is in
PU shutdown mode. VCO’s, Crystal, and outputs are turned off.
13, 21
VDD
- P - 3.3 volt power supply for core logic.
3, 12,
14, 20,
VSS
- P - Ground pins for the device.
22, 28
9, 6 VDDP
- P - 3.3 Volt power supply pins for PCI (1:5) and PCI_F clock output
buffers.
25 VDDC - P - 3.3 or 2.5 Volt power supply for CPUCLK (0:1) outputs.
27 VDDR - P
3.3 Volt power supply pins for reference clock output buffers
and crystal circuit.
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07016 Rev. **
5/17/2001
Page 2 of 10


Part Number SG556
Description Mobile Pentium Processor Application Clock Generator
Maker Cypress Semiconductor
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