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GVT7C1362A - 256K x 36 / 512K x 18 Pipelined SRAM

Download the GVT7C1362A datasheet PDF. This datasheet also covers the GVT71256D36 variant, as both devices belong to the same 256k x 36 / 512k x 18 pipelined sram family and are provided as variant models within a single manufacturer datasheet.

General Description

The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology.

Each memory cell consists of four transistors and two high-valued resistors.

Key Features

  • Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns Fast clock speed: 225, 200, 166, and 150 MHz Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns Optimal for depth expansion (one cycle chip deselect to eliminate bus contention) 3.3V.
  • 5% and +10% power supply 3.3V or 2.5V I/O supply 5V tolerant inputs except I/Os Clam.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (GVT71256D36_CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer

Other Datasheets by Cypress (Infineon)

Part Number Description
GVT7C1360A 256K x 36 / 512K x 18 Pipelined SRAM
GVT7C1361A 256K x 36 / 512K x 18 Sunchronous Burse Flowthrough SRAM
GVT7C1363A 256K x 36 / 512K x 18 Sunchronous Burse Flowthrough SRAM
GVT7C1366A 256K X 36/512K X 18 Pipelined SRAM
GVT7C1367A 256K X 36/512K X 18 Pipelined SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
( DataSheet : www.DataSheet4U.com ) 1CY7C1329 PRELIMINARY CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 256K x 36/512K x 18 Pipelined SRAM Features • • • • • • • • • • • • • • • • • • Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns Fast clock speed: 225, 200, 166, and 150 MHz Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns Optimal for depth expansion (one cycle chip deselect to eliminate bus contention) 3.3V –5% and +10% power supply 3.3V or 2.