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GVT7C1359A - 256K X 18 Synchronous-pipelined Cache Tag RAM

Download the GVT7C1359A datasheet PDF. This datasheet also covers the GVT71256T18 variant, as both devices belong to the same 256k x 18 synchronous-pipelined cache tag ram family and are provided as variant models within a single manufacturer datasheet.

General Description

The Cypress Synchronous Burst SRAM family employs high-speed, low power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology.

Each memory cell consists of four transistors and two high valued resistors.

Key Features

  • Fast match times: 3.5, 3.8, 4.0 and 4.5 ns Fast clock speed: 166, 150, 133, and 100 MHz Fast OE access times: 3.5, 3.8, 4.0 and 5.0 ns Pipelined data comparator Data input register load control by DEN Optimal for depth expansion (one cycle chip deselect to eliminate bus contention) 3.3V.
  • 5% and +10% c.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (GVT71256T18_CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer

Other Datasheets by Cypress (Infineon)

Part Number Description
GVT7C1354A 256Kx36/512Kx18 Pipelined SRAM
GVT7C1355A 256K x 36 / 512K x 18 Flow Thru SRAM
GVT7C1356A 256Kx36/512Kx18 Pipelined SRAM
GVT7C1357A 256K x 36 / 512K x 18 Flow Thru SRAM
GVT7C1325A 256K x 18 Synchronous Flow Through Burst SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
( DataSheet : www.DataSheet4U.com ) 327 CY7C1359A/GVT71256T18 256K x 18 Synchronous-Pipelined Cache Tag RAM Features • • • • • • • • • • • • • • • • • • • Fast match times: 3.5, 3.8, 4.0 and 4.5 ns Fast clock speed: 166, 150, 133, and 100 MHz Fast OE access times: 3.5, 3.8, 4.0 and 5.0 ns Pipelined data comparator Data input register load control by DEN Optimal for depth expansion (one cycle chip deselect to eliminate bus contention) 3.3V –5% and +10% core power supply 2.5V or 3.