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GVT7C1356A - 256Kx36/512Kx18 Pipelined SRAM

Download the GVT7C1356A datasheet PDF. This datasheet also covers the GVT71256ZC36 variant, as both devices belong to the same 256kx36/512kx18 pipelined sram family and are provided as variant models within a single manufacturer datasheet.

General Description

The CY7C1354A/GVT71256ZC36 and CY7C1356A/ GVT71512ZC18 SRAMs are designed to eliminate dead cycles when transitioning from Read to Write or vice versa.

These SRAMs are optimized for 100% bus utilization and achieve Zero Bus Latency (ZBL)/No Bus Latency (NoBL).

Key Features

  • Zero Bus Latency, no dead cycles between Write and Read cycles.
  • Fast clock speed: 200, 166, 133, 100 MHz.
  • Fast access time: 3.2, 3.6, 4.2, 5.0 ns.
  • Internally synchronized registered outputs eliminate the need to control OE.
  • Single 3.3V.
  • 5% and +5% power supply VCC.
  • Separate VCCQ for 3.3V or 2.5V I/O.
  • Single WEN (Read/Write) control pin.
  • Positive clock-edge triggered, address, data, and control signal registers for f.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (GVT71256ZC36_CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer

Other Datasheets by Cypress (Infineon)

Part Number Description
GVT7C1354A 256Kx36/512Kx18 Pipelined SRAM
GVT7C1355A 256K x 36 / 512K x 18 Flow Thru SRAM
GVT7C1357A 256K x 36 / 512K x 18 Flow Thru SRAM
GVT7C1359A 256K X 18 Synchronous-pipelined Cache Tag RAM
GVT7C1325A 256K x 18 Synchronous Flow Through Burst SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
( DataSheet : www.DataSheet4U.com ) CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 256K x 36/512K x 18 Pipelined SRAM with NoBL™ Architecture Features • Zero Bus Latency, no dead cycles between Write and Read cycles • Fast clock speed: 200, 166, 133, 100 MHz • Fast access time: 3.2, 3.6, 4.2, 5.0 ns • Internally synchronized registered outputs eliminate the need to control OE • Single 3.3V –5% and +5% power supply VCC • Separate VCCQ for 3.3V or 2.