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GVT71512ZB18 - 256K x 36 / 512K x 18 Flow Thru SRAM

Download the GVT71512ZB18 datasheet PDF. This datasheet also covers the GVT71256ZB36 variant, as both devices belong to the same 256k x 36 / 512k x 18 flow thru sram family and are provided as variant models within a single manufacturer datasheet.

General Description

The CY7C1355A/GVT71256ZB36 and CY7C1357A/ GVT71512ZB18 SRAMs are designed to eliminate dead cycles when transitions from READ to WRITE or vice versa.

These SRAMs are optimized for 100 percent bus utilization and achieves Zero Bus Latency (ZBL)/No Bus Latency (NoBL).

Key Features

  • Zero Bus Latency, no dead cycles between write and read cycles.
  • Fast clock speed: 133, 117, and 100 MHz.
  • Fast access time: 6.5, 7.0, 7.5, and 8.0 ns.
  • Internally synchronized registered outputs eliminate the need to control OE.
  • Single 3.3V.
  • 5% and +5% power supply VCC.
  • Separate VCCQ for 3.3V or 2.5V I/O.
  • Single R/W (READ/WRITE) control pin.
  • Positive clock-edge triggered, address, data, and control signal registers fo.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (GVT71256ZB36_CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer

Other Datasheets by Cypress (Infineon)

Part Number Description
GVT71512ZC18 256Kx36/512Kx18 Pipelined SRAM
GVT71512B18 256K x 36 / 512K x 18 Sunchronous Burse Flowthrough SRAM
GVT71512C18 256K X 36/512K X 18 Pipelined SRAM
GVT71512D18 256K x 36 / 512K x 18 Pipelined SRAM
GVT71256B36 (GVT7xxxx) 256K x 36 / 512K x 18 Sunchronous Burse Flowthrough SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
( DataSheet : www.DataSheet4U.com ) 1CY7C1357A PRELIMINARY CY7C1355A/GVT71256ZB36 CY7C1357A/GVT71512ZB18 256Kx36/512Kx18 Flow-Thru SRAM with NoBL™ Architecture Features • Zero Bus Latency, no dead cycles between write and read cycles • Fast clock speed: 133, 117, and 100 MHz • Fast access time: 6.5, 7.0, 7.5, and 8.0 ns • Internally synchronized registered outputs eliminate the need to control OE • Single 3.3V –5% and +5% power supply VCC • Separate VCCQ for 3.3V or 2.