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Cypress Semiconductor Electronic Components Datasheet

CYDM256B16 Datasheet

1.8 V 4 K/8 K/16 K x 16 MoBL Dual-Port Static RAM

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CYDM064B16
CYDM128B16
CYDM256B16
1.8 V, 4K/8K/16K × 16 MoBL® Dual-Port
Static RAM
1.8 V, 4K/8K/16K × 16 MoBL® Dual-Port Static RAM
Features
True dual ported memory cells that allow simultaneous access
of the same memory location
4, 8, or 16K × 16 organization
Ultra Low operating power
Active: ICC = 15 mA (typical) at 55 ns
Standby: ISB3 = 2 A (typical)
Small footprint: available in a 6 × 6 mm 100-pin Pb-free vfBGA
Port independent 1.8 V, 2.5 V, and 3.0 V I/Os
Full asynchronous operation
Automatic power down
Pin select for Master or Slave
Expandable data bus to 32-bits with Master or Slave chip select
when using more than one device
On-chip arbitration logic
Semaphores included to permit software handshaking
between ports
Input read registers and output drive registers
INT flag for port-to-port communication
Separate upper-byte and lower-byte control
Industrial temperature ranges
Functional Description
The CYDM256B16, CYDM128B16, and CYDM064B16 are low
power CMOS 4K, 8K,16K × 16 dual-port static RAMs. Arbitration
schemes are included on the devices to handle situations when
multiple processors access the same piece of data. Two ports
are provided that permit independent, asynchronous access for
reads and writes to any location in memory. The devices can be
used as standalone 16-bit dual-port static RAMs or multiple
devices can be combined to function as a 32-bit or wider
master/slave dual-port static RAM. An M/S pin is provided for
implementing 32-bit or wider memory applications without the
need for separate master and slave devices or additional
discrete logic. Application areas include interprocessor or multi-
processor designs, communications status buffering, and
dual-port video or graphics memory.
Each port has independent control pins: Chip Enable (CE), Read
or Write Enable (R/W), and Output Enable (OE). Two flags are
provided on each port (BUSY and INT). BUSY indicates that the
port is trying to access the same location currently being
accessed by the other port. The Interrupt flag (INT) permits
communication between ports or systems through a mail box.
The semaphores are used to pass a flag or token, from one port
to the other, to indicate that a shared resource is in use. The
semaphore logic consists of eight shared latches. Only one side
can control the latch (semaphore) at any time. Control of a
semaphore indicates that a shared resource is in use. An
automatic power down feature is controlled independently on
each port by a Chip Enable (CE) pin.
The CYDM256B16, CYDM128B16, CYDM064B16 are available
in 100-ball 0.5 mm pitch Ball Grid Array (BGA) packages.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-00217 Rev. *K
• San Jose, CA 95134-1709 • 408-943-2600
Revised April 12, 2018


Cypress Semiconductor Electronic Components Datasheet

CYDM256B16 Datasheet

1.8 V 4 K/8 K/16 K x 16 MoBL Dual-Port Static RAM

No Preview Available !

CYDM064B16
CYDM128B16
CYDM256B16
Selection Guide for VCC = 1.8V
Parameter
CYDM256B16/CYDM128B16/CYDM064B16
(-55)
Port I/O Voltages (P1–P2)
1.8 V–1.8 V
Maximum Access Time
55
Typical Operating Current
15
Typical Standby Current for ISB1
Typical Standby Current for ISB3
2
2
Selection Guide for VCC = 2.5 V
Parameter
CYDM256B16/CYDM128B16/CYDM064B16
(-55)
Port I/O Voltages (P1–P2)
2.5 V–2.5 V
Maximum Access Time
55
Typical Operating Current
28
Typical Standby Current for ISB1
Typical Standby Current for ISB3
6
4
Selection Guide for VCC = 3.0 V
Parameter
CYDM256B16/CYDM128B16/CYDM064B16
(-55)
Port I/O Voltages (P1–P2)
3.0 V–3.0 V
Maximum Access Time
55
Typical Operating Current
42
Typical Standby Current for ISB1
Typical Standby Current for ISB3
7
6
Unit
V
ns
mA
A
A
Unit
V
ns
mA
A
A
Unit
V
ns
mA
A
A
Document Number: 001-00217 Rev. *K
Page 2 of 33


Part Number CYDM256B16
Description 1.8 V 4 K/8 K/16 K x 16 MoBL Dual-Port Static RAM
Maker Cypress Semiconductor
Total Page 30 Pages
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