CY7C9689 Datasheet | Cypress

Features Second-generation HOTLink® technology AMD™ AM7968/7969 TAXIchip™ patible 8-bit 4B/5B or 10-bit 5B/6B NRZI encoded data transport 10-bit or 12-bit NRZI pre-encoded (bypass) data transport - Synchronous TTL parallel interface - Embedded/Bypassable 256 character Transmit and Receive FIFOs - 50-to-200 MBaud serial signaling rate - Internal PLLs with no external PLL ponents - Dual differential PECL-patible serial inputs and outputs - patible with fiber-optic modules and copper cables .. - Built-In Self-Test (BIST) for link testing - Link Quality Indicator - Single +5.0V ±10%supply - 100-pin TQFP - - - - improve its serial transmission characteristics. These encoded characters are then serialized, converted to NRZI, and output from two PECL-patible differential transmission line drivers at a bit-rate of either 10 or 20 times the input reference clock in 8-bit (or 10-bit bypass) mode, or 12 or 24 times the reference clock in 10-bit (or 12-bit bypass) mode. The receive section of the CY7C9689 HOTLink accepts a serial bit-stream from one of two PECL patible differential line receivers and, using a pletely integrated PLL Clock Synchronizer, recovers the timing information necessary for data reconstruction. The recovered bit stream is converted from NRZI to NRZ, deserialized, framed into characters, 4B/5B or 5B/6B decoded, and checked for transmission errors. The recovered 8- or 10-bit decoded characters are then written to an internal Receive FIFO, and presented to the destination host system. The integrated 4B/5B and 5B/6B encoder/decoder may be bypassed (disabled) for systems that present externally encoded or scrambled data at the parallel interface. With the encoder bypassed, the pre-encoded parallel data stream is converted to and from a serial NRZI stream. The embedded FIFOs may also be bypassed (disabled) to create a reference-locked serial transmission link. For those systems requiring even greater FIFO storage capability, external FIFOs may be directly...