CY7C68000A
Overview
- Supports transmission of Resume Signaling 3.3V Operation Two package options: 56-pin QFN and 56-pin VFBGA All required terminations, including 1.5 Kohm pull up on DPLUS, are internal to chip Supports USB 2.0 Test Modes UTMI-compliant and USB 2.0 certified for device operation Operates in both USB 2.0 High Speed (HS), 480 Mbits/second, and Full Speed (FS), 12 Mbits/second Optimized for Seamless Interface with Intel Monahans Applications Processors Tri-state Mode enables sharing of UTMI Bus with other devices Serial-to-Parallel and Parallel-to-Serial Conversions 8-bit Unidirectional, 8-bit Bidirectional, or 16-bit Bidirectional External Data Interface Synchronous Field and EOP Detection on Receive Packets Synchronous Field and EOP Generation on Transmit Packets Data and Clock Recovery from the USB Serial Stream Bit stuffing and unstuffing; Bit Stuff Error Detection Staging Register to manage Data Rate variation due to Bit stuffing and unstuffing 16-bit 30 MHz and 8-bit 60 MHz Parallel Interface Ability to switch between FS and HS terminations and signaling Supports detection of USB Reset, Suspend, and Resume Supports HS identification and detection as defined by the USB 2.0 Specification ® The Cypress MoBL-USB TX2 is a Universal Serial Bus (USB) specification revision 2.0 transceiver, serial and deserializer, to a parallel interface of either 16 bits at 30 MHz or eight bits at 60 MHz. The MoBL-USB TX2 provides a high speed physical layer interface that operates at the maximum allowable USB 2.0 bandwidth. This enables the system designer to keep the complex high speed analog USB components external to the digital ASIC. This decreases development time and associated risk. A standard USB 2.0-certified interface is provided and is compliant with Transceiver Macrocell Interface (UTMI) specific
