CY7C4255
Features
- High-speed, low-power, first-in first-out (FIFO) memories
- 8K x 18 (CY7C4255)
- 16K x 18 (CY7C4265)
- 0.5 micron CMOS for optimum speed/power
- High-speed 100-MHz operation (10 ns read/write cycle times)
- Low power
- ICC=45 m A
- Fully asynchronous and simultaneous read and write operation
- Empty, Full, Half Full, and programmable Almost Empty and Almost Full status flags
- TTL patible
- Retransmit function
- Output Enable (OE) pins
- Independent read and write enable pins
- Center power and ground pins for reduced noise
- Supports free-running 50% duty cycle clock inputs
- Width Expansion Capability
- Depth Expansion Capability
- 64-pin PLCC and 64-pin TQFP
- Pin-patible density upgrade to CY7C42X5 family
- Pin-patible density upgrade to IDT72205/15/25/35/45 are 18 bits wide and are pin/functionally patible to the CY7C42X5 Synchronous FIFO family. The CY7C4255/65 can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags. These...
