CY7C335 Description
The CY7C335 is a high-performance, erasable, programmable logic device (EPLD) whose architecture has been optimized to enable the user to easily and efficiently construct very high performance state machines. The architecture of the CY7C335, consisting of the user-configurable output macrocell, bidirectional I/O capability, input registers, and three separate clocks, enables the user to design high-performance state...
CY7C335 Key Features
- 100-MHz output registered operation
- Twelve I/O macrocells, each having
- Registered, three-state I/O pins
- Input and output register clock select multiplexer
- Feed back multiplexer
- Output enable (OE) multiplexer Bypass on input and output registers All twelve macrocell state registers can be hidden U
- 2-ns input set-up and 9-ns output register clock to output
- 10-ns input register clock to state register clock
- 28-pin, 300-mil DIP, LCC, PLCC
- Erasable and reprogrammable