CY7C2561KV18 architecture equivalent, 72-mbit qdr-ii sram 4-word burst architecture.
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Configurations
With Read Cycle Latency of 2.5 cycles: CY7C2561KV18
– 8M x 8 CY7C2576KV18
– 8M x 9 CY7C2563KV18
– 4M.
The CY7C2561KV18, CY7C2576KV18, CY7C2563KV18, and CY7C2565KV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II+ architecture. Similar to QDR-II architecture, QDR-II+ architecture consists of two separate ports: the read port and the write .
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