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Cypress Semiconductor Electronic Components Datasheet

CY7C245A Datasheet

2K x 8 Reprogrammable Registered PROM

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CY7C245A
2K x 8 Reprogrammable Registered PROM
Features
• Windowed for reprogrammability
• CMOS for optimum speed/power
• High speed
15-ns address set-up
10-ns clock to output
• Low power
330 mW (commercial) for -25 ns
660 mW (military)
• Programmable synchronous or asynchronous output
enable
• On-chip edge-triggered registers
• Programmable asynchronous register (INIT)
• EPROM technology, 100% programmable
• Slim, 300-mil, 24-pin plastic or hermetic DIP
• 5V ±10% VCC, commercial and military
• TTL-compatible I/O
• Direct replacement for bipolar PROMs
• Capable of withstanding greater than 2001V static
discharge
Logic Block Diagram
INIT
A0
A1
A2
A3
ROW
ADDRESS
PROGRAMMABLE
ARRAY
MULTIPLEXER
A4
A5
A6
ADDRESS
DECODER
A7
A8
A9 COLUMN
ADDRESS
A10
E/E S
CP
PROGRAMMABLE
DQ
MULTIPLEXER
C
Functional Description
The CY7C245A is a high-performance, 2K x 8, electrically
programmable, read-only memory packaged in a slim 300-mil
plastic or hermetic DIP. The ceramic package may be
equipped with an erasure window; when exposed to UV light
the PROM is erased and can then be reprogrammed. The
memory cells utilize proven EPROM floating-gate technology
and byte-wide intelligent programming algorithms.
The CY7C245A replaces bipolar devices and offers the advan-
tages of lower power, reprogrammability, superior perfor-
mance and high programming yield. The EPROM cell requires
only 12.5V for the supervoltage, and low current requirements
allow gang programming. The EPROM cells allow each
memory location to be tested 100%, because each location is
written into, erased, and repeatedly exercised prior to encap-
sulation. Each PROM is also tested for AC performance to
guarantee that after customer programming the product will
meet AC specification limits.
The CY7C245A has an asynchronous initialize function (INIT).
This function acts as a 2049th 8-bit word loaded into the
on-chip register. It is user programmable with any desired
word, or may be used as a PRESET or CLEAR function on the
outputs. INIT is triggered by a low level, not an edge.
8-BIT
EDGE-
TRIGGERED
REGISTER
CP
Pin Configurations
DIP Top View
O
A7 1
24 VCC
7
O
A6 2
A5 3
23 A8
22 A9
A4 4
21 A10
6
O
A3 5
A2 6
20 INIT
19 E/ES
5
O
A1 7
A0 8
18 CP
17 O7
4
O0 9
16 O6
O
O1 10
15 O5
3
O2 11
14 O4
O
GND 12
13 O3
2 LCC/PLCC (Opaque only) Top View
O
1
O
4 3 2 1 282726
A4 5
25 A10
0
A3 6
A2 7
A1 8
24 INIT
23
22
EC/PES
A0 9
21 NC
NC
O0
10 20
111213141516171819
O7
O6
Selection Guide
Minimum Address Set-up Time
Maximum Clock to Output
Maximum Operating Current Standard
Commercial
Military
7C245A-15
15
10
120
7C245A-18
18
12
120
120
7C245A-25
25
12
90
120
7C245A-35
35
15
90
120
Unit
ns
ns
mA
mA
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-04007 Rev. *D
Revised November 4, 2003


Cypress Semiconductor Electronic Components Datasheet

CY7C245A Datasheet

2K x 8 Reprogrammable Registered PROM

No Preview Available !

CY7C245A
Operating Modes
The CY7C245A is a CMOS electrically programmable read
only memory organized as 2048 words x 8 bits and is a
pin-for-pin replacement for bipolar TTL fusible link PROMs.
The CY7C245A incorporates a D-type, master-slave register
on chip, reducing the cost and size of pipelined micropro-
grammed systems and applications where accessed PROM
data is stored temporarily in a register. Additional flexibility is
provided with a programmable synchronous (ES) or
asynchronous (E) output enable and asynchronous initial-
ization (INIT).
Upon power-up the state of the outputs will depend on the
programmed state of the enable function (ES or E). If the
synchronous enable (ES) has been programmed, the register
will be in the set condition causing the outputs (O0–O7) to be
in the OFF or high-impedance state. If the asynchronous
enable (E) is being used, the outputs will come up in the OFF
or high-impedance state only if the enable (E) input is at a
HIGH logic level. Data is read by applying the memory location
to the address inputs (A0–A10) and a logic LOW to the enable
input. The stored data is accessed and loaded into the master
flip-flops of the data register during the address set-up time. At
the next LOW-to-HIGH transition of the clock (CP), data is
transferred to the slave flip-flops, which drive the output
buffers, and the accessed data will appear at the outputs
(O0–O7).
If the asynchronous enable (E) is being used, the outputs may
be disabled at any time by switching the enable to a logic
HIGH, and may be returned to the active state by switching the
enable to a logic LOW.
If the synchronous enable (ES) is being used, the outputs will
go to the OFF or high-impedance state upon the next positive
clock edge after the synchronous enable input is switched to
a HIGH level. If the synchronous enable pin is switched to a
logic LOW, the subsequent positive clock edge will return the
output to the active state. Following a positive clock edge, the
address and synchronous enable inputs are free to change
since no change in the output will occur until the next
low-to-high transition of the clock. This unique feature allows
the CY7C245A decoders and sense amplifiers to access the
next location while previously addressed data remains stable
on the outputs.
System timing is simplified in that the on-chip edge triggered
register allows the PROM clock to be derived directly from the
system clock without introducing race conditions. The on-chip
register timing requirements are similar to those of discrete
registers available in the market.
The CY7C245A has an asynchronous initialize input (INIT).
The initialize function is useful during power-up and time-out
sequences and can facilitate implementation of other sophis-
ticated functions such as a built-in “jump start” address. When
activated, the initialize control input causes the contents of a
user-programmed 2049th 8-bit word to be loaded into the
on-chip register. Each bit is programmable and the initialize
function can be used to load any desired combination of 1s
and 0s into the register. In the unprogrammed state, activating
INIT will generate a register CLEAR (all outputs LOW). If all
the bits of the initialize word are programmed, activating INIT
performs a register PRESET (all outputs HIGH).
Applying a LOW to the INIT input causes an immediate load
of the programmed initialize word into the master and slave
flip-flops of the register, independent of all other inputs,
including the clock (CP). The initialize data will appear at the
device outputs after the outputs are enabled by bringing the
asynchronous enable (E) LOW.
Erasure Characteristics
Wavelengths of light less than 4000 Angstroms begin to erase
the 7C245A. For this reason, an opaque label should be
placed over the window if the PROM is exposed to sunlight or
fluorescent lighting for extended periods of time.
The recommended dose for erasure is ultraviolet light with a
wavelength of 2537 Angstroms for a minimum dose (UV
intensity multiplied by exposure time) of 25 Wsec/cm2. For an
ultraviolet lamp with a 12 mW/cm2 power rating the exposure
time would be approximately 35 minutes. The 7C245A needs
to be within 1 inch of the lamp during erasure. Permanent
damage may result if the PROM is exposed to high-intensity
UV light for an extended period of time. 7258 Wsec/cm2 is the
recommended maximum dosage.
Programming Information
Programming support is available from Cypress as well as
from a number of third-party software vendors. For detailed
programming information, including a listing of software
packages, please see the PROM Programming Information
located at the end of this section. Programming algorithms can
be obtained from any Cypress representative.
Bit Map Data
Programmer Address
RAM Data
Decimal
Hex
Contents
00
Data
..
..
..
.
.
.
2047
7FF
Data
2048
800
Init Byte
2049
801 Control Byte
Control Byte
00 Asynchronous output enable (default state)
01 Synchronous output enable
Document #: 38-04007 Rev. *D
Page 2 of 12


Part Number CY7C245A
Description 2K x 8 Reprogrammable Registered PROM
Maker Cypress Semiconductor
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