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CY7C2263KV18 Datasheet 36-Mbit QDR II+ SRAM Four-Word Burst Architecture

Manufacturer: Cypress (now Infineon)

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Overview

CY7C2263KV18/CY7C2265KV18 36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.

Key Features

  • Separate independent read and write data ports.
  • Supports concurrent transactions.
  • 550 MHz clock for high bandwidth.
  • Four-word burst for reducing address bus frequency.
  • Double data rate (DDR) interfaces on both read and write ports (data transferred at 1100 MHz) at 550 MHz.
  • Available in 2.5 clock cycle latency.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Echo clocks (CQ and CQ) simplify data capture in high spe.

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