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CY7C2165KV18 Datasheet 18-Mbit QDR II+ SRAM Four-Word Burst Architecture

Manufacturer: Cypress (now Infineon)

Download the CY7C2165KV18 datasheet PDF. This datasheet also includes the CY7C2163KV18 variant, as both parts are published together in a single manufacturer document.

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Note: The manufacturer provides a single datasheet file (CY7C2163KV18-CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

Overview

CY7C2163KV18/CY7C2165KV18 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.

Key Features

  • Separate independent read and write data ports.
  • Supports concurrent transactions.
  • 550-MHz clock for high bandwidth.
  • Four-word burst for reducing address bus frequency.
  • Double data rate (DDR) interfaces on both read and write ports (data transferred at 1100 MHz) at 550 MHz.
  • Available in 2.5 clock cycle latency.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Echo clocks (CQ and CQ) simplify data capture in high-speed.

More Datasheets from Cypress (now Infineon)

Part Number Description
CY7C2163KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture
CY7C2168KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture
CY7C2170KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture
CY7C2245KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture
CY7C225A 512 x 8 Registered PROM
CY7C2262XV18 36-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture
CY7C2263KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture
CY7C2263XV18 36-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture
CY7C2264XV18 36-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture
CY7C2265KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture