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Cypress Semiconductor Electronic Components Datasheet

CY7C2165KV18 Datasheet

18-Mbit QDR II+ SRAM Four-Word Burst Architecture

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CY7C2163KV18/CY7C2165KV18
18-Mbit QDR® II+ SRAM Four-Word
Burst Architecture (2.5 Cycle Read Latency) with ODT
18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
Features
Separate independent read and write data ports
Supports concurrent transactions
550-MHz clock for high bandwidth
Four-word burst for reducing address bus frequency
Double data rate (DDR) interfaces on both read and write ports
(data transferred at 1100 MHz) at 550 MHz
Available in 2.5 clock cycle latency
Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
Data valid pin (QVLD) to indicate valid data on the output
On-die termination (ODT) feature
Supported for D[x:0], BWS[x:0], and K/K inputs
Single multiplexed address input bus latches address inputs
for read and write ports
Separate port selects for depth expansion
Synchronous internally self-timed writes
QDR® II+ operates with 2.5 cycle read latency when DOFF is
asserted HIGH
Operates similar to QDR I device with one cycle read latency
when DOFF is asserted LOW
Available in × 18 and × 36 configurations
Full data coherency, providing most current data
Core VDD = 1.8 V± 0.1 V; I/O VDDQ = 1.4 V to VDD [1]
Supports both 1.5 V and 1.8 V I/O supply
HSTL inputs and variable drive HSTL output buffers
Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
CY7C2163KV18 offered in Pb-free packages and
CY7C2165KV18 offered in non Pb-free packages
JTAG 1149.1 compatible test access port
Phase-locked loop (PLL) for accurate data placement
Selection Guide
Maximum operating frequency
Maximum operating current
Description
Configurations
With Read Cycle Latency of 2.5 cycles:
CY7C2163KV18 – 1 M × 18
CY7C2165KV18 – 512 K × 36
Functional Description
The CY7C2163KV18, and CY7C2165KV18 are 1.8 V
synchronous pipelined SRAMs, equipped with QDR II+
architecture. Similar to QDR II architecture, QDR II+ architecture
consists of two separate ports: the read port and the write port to
access the memory array. The read port has dedicated data
outputs to support read operations and the write port has
dedicated data inputs to support write operations. QDR II+
architecture has separate data inputs and data outputs to
completely eliminate the need to ‘turnaround’ the data bus that
exists with common I/O devices. Each port is accessed through
a common address bus. Addresses for read and write addresses
are latched on alternate rising edges of the input (K) clock.
Accesses to the QDR II+ read and write ports are completely
independent of one another. To maximize data throughput, both
read and write ports are equipped with DDR interfaces. Each
address location is associated with four 18-bit words
(CY7C2163KV18), or 36-bit words (CY7C2165KV18) that burst
sequentially into or out of the device. Because data is transferred
into and out of the device on every rising edge of both input
clocks (K and K), memory bandwidth is maximized while
simplifying system design by eliminating bus ‘turn-arounds’.
These devices have an ODT feature supported for D[x:0],
BWS[x:0], and K/K inputs, which helps eliminate external
termination resistors, reduce cost, reduce board area, and
simplify board routing.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
For a complete list of related resources, click here.
550 MHz 450 MHz Unit
550 450 MHz
× 18 780
670 mA
× 36 1100
930
Note
1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support VDDQ = 1.4 V to VDD.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-58921 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised December 31, 2015


Cypress Semiconductor Electronic Components Datasheet

CY7C2165KV18 Datasheet

18-Mbit QDR II+ SRAM Four-Word Burst Architecture

No Preview Available !

CY7C2163KV18/CY7C2165KV18
Logic Block Diagram – CY7C2163KV18
D[17:0]
18
A(17:0) 18
Address
Register
Write Write Write Write
Reg Reg Reg Reg
Address
Register
18 A(17:0)
K
K
DOFF
VREF
WPS
BWS[1:0]
CLK
Gen.
Control
Logic
Read Data Reg.
72
36
36
Control
Logic
RPS
Reg.
Reg.
Reg. 18
18
18
18
18
CQ
CQ
Q[17:0]
QVLD
Logic Block Diagram – CY7C2165KV18
D[35:0]
36
A(16:0) 17
Address
Register
Write Write Write Write
Reg Reg Reg Reg
Address
Register
17 A(16:0)
K
K
DOFF
VREF
WPS
BWS[3:0]
CLK
Gen.
Control
Logic
Read Data Reg.
144
72
72
Control
Logic
RPS
Reg.
Reg.
Reg. 36
36
36
36
36
CQ
CQ
Q[35:0]
QVLD
Document Number: 001-58921 Rev. *J
Page 2 of 31


Part Number CY7C2165KV18
Description 18-Mbit QDR II+ SRAM Four-Word Burst Architecture
Maker Cypress Semiconductor
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