fax id: 10131bCY7C185
FOR REVIEW ONLY
CY7C185
8K x 8 Static RAM
Features
• High speed
— 15 ns
• Fast tDOE
• Low active power
— 715 mW
• Low standby power
— 220 mW
• CMOS for optimum speed/power
• Easy memory expansion with CE1, CE2 and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
Functional Description
The CY7C185 is a high-performance CMOS static RAM orga-
nized as 8192 words by 8 bits. Easy memory expansion is
Logic Block Diagram
provided by an active LOW chip enable (CE1), an active HIGH
chip enable (CE2), and active LOW output enable (OE) and
three-state drivers. This device has an automatic power-down
feature (CE1 or CE2), reducing the power consumption by 70%
when deselected. The CY7C185 is in a standard 300-mil-wide
DIP and SOJ package.
An active LOW write enable signal (WE) controls the writ-
ing/reading operation of the memory. When CE1 and WE in-
puts are both LOW and CE2 is HIGH, data on the eight data
input/output pins (I/O0 through I/O7) is written into the memory
location addressed by the address present on the address
pins (A0 through A12). Reading the device is accomplished by
selecting the device and enabling the outputs, CE1 and OE
active LOW, CE2 active HIGH, while WE remains inactive or
HIGH. Under these conditions, the contents of the location ad-
dressed by the information on address pins are present on the
eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH. A die coat is used to insure alpha immunity.
Pin Configurations
INPUT BUFFER
I/O0
I/O1
A1
A2
A3
A4
A5
A6
A7
A8
CE1
CE2
WE
OE
256 x 32 x 8
ARRAY
POWER
COLUMN DECODER DOWN
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
Selection Guide[1]
7C185–12
7C185–15
Maximum Access Time (ns)
12 15
Maximum Operating Current (mA)
140
130
Maximum Standby Current (mA)
40/15
40/15
Shaded areas contain preliminary information.
Note:
1. For military specifications, see the CY7C185A/CY7C186A datasheet.
C185–1
7C185–20
20
110
20/15
DIP/SOJ
Top View
NC
A4
A5
A6
A7
A8
A9
A10
A11
A12
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VCC
27 WE
26 CE2
25 A3
24 A2
23 A1
22 OE
21 A0
20 CE1
19 I/O7
18 I/O6
17 I/O5
16 I/O4
15 I/O3
C185–2
7C185–25
25
100
20/15
7C185–35
35
100
20/15
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
May 1986 – Revised April 1996
