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CY7C1645KV18 Datasheet 144-Mbit QDR II+ SRAM Four-Word Burst Architecture

Manufacturer: Cypress (now Infineon)

Overview: CY7C1643KV18/CY7C1645KV18 144-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) 144-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.

Download the CY7C1645KV18 datasheet PDF. This datasheet also includes the CY7C1643KV18 variant, as both parts are published together in a single manufacturer document.

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Key Features

  • Separate independent read and write data ports.
  • Supports concurrent transactions.
  • 450-MHz clock for high bandwidth.
  • Four-word burst for reducing address bus frequency.
  • Double data rate (DDR) interfaces on both read and write ports (data transferred at 900 MHz) at 450 MHz.
  • Available in 2.0-clock cycle latency.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Echo clocks (CQ and CQ) simplify data capture in high-speed sys.

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