CY7C1615KV18 Description
CY7C1613KV18/CY7C1615KV18 144-Mbit QDR® II SRAM Four-Word Burst Architecture 144-Mbit QDR® II SRAM Four-Word Burst Architecture.
CY7C1615KV18 Key Features
- Separate independent read and write data ports
- Supports concurrent transactions
- 333 MHz clock for high bandwidth
- Four-word burst for reducing address bus frequency
- Double Data Rate (DDR) interfaces on both read and write ports
- Two input clocks (K and K) for precise DDR timing
- SRAM uses rising edges only
- Two input clocks for output data (C and C) to minimize clock
- Echo clocks (CQ and CQ) simplify data capture in high speed
- Single multiplexed address input bus latches address inputs