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CY7C1612KV18 - 144-Mbit QDR II SRAM Two-Word Burst Architecture

Download the CY7C1612KV18 datasheet PDF. This datasheet also covers the CY7C1625KV18 variant, as both devices belong to the same 144-mbit qdr ii sram two-word burst architecture family and are provided as variant models within a single manufacturer datasheet.

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Note: The manufacturer provides a single datasheet file (CY7C1625KV18-CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

Overview

CY7C1625KV18 CY7C1612KV18 CY7C1614KV18 144-Mbit QDR® II SRAM Two-Word Burst Architecture 144-Mbit QDR® II SRAM Two-Word Burst.

Key Features

  • Separate independent read and write data ports.
  • Supports concurrent transactions.
  • 360-MHz clock for high bandwidth.
  • Two-word burst on all accesses.
  • Double data rate (DDR) interfaces on both read and write ports (data transferred at 720 MHz) at 360 MHz.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
  • Echo clocks (CQ and CQ) sim.

More Datasheets from Cypress (now Infineon)

Part Number Description
CY7C1613KV18 144-Mbit QDR II SRAM Four-Word Burst Architecture
CY7C1614KV18 144-Mbit QDR II SRAM Two-Word Burst Architecture
CY7C1615KV18 144-Mbit QDR II SRAM Four-Word Burst Architecture
CY7C1618KV18 144-Mbit DDR II SRAM Two-Word Burst Architecture
CY7C1620KV18 144-Mbit DDR II SRAM Two-Word Burst Architecture
CY7C1625KV18 144-Mbit QDR II SRAM Two-Word Burst Architecture
CY7C164 16K x 4 Static RAM
CY7C1643KV18 144-Mbit QDR II+ SRAM Four-Word Burst Architecture
CY7C1645KV18 144-Mbit QDR II+ SRAM Four-Word Burst Architecture
CY7C1648KV18 144-Mbit DDR II+ SRAM Two-Word Burst Architecture