CY7C1612KV18, CY7C1625KV18 - 144-Mbit QDR II SRAM Two-Word Burst Architecture

Cypress Semiconductor

Datasheet Details

Part number	CY7C1612KV18, CY7C1625KV18
Manufacturer	Cypress Semiconductor
File Size	593.44 KB
Description	144-Mbit QDR II SRAM Two-Word Burst Architecture
Datasheet	CY7C1625KV18-CypressSemiconductor.pdf
Note	This datasheet PDF includes multiple part numbers: CY7C1612KV18, CY7C1625KV18. Please refer to the document for exact specifications by model.

Separate independent read and write data ports.
Supports concurrent transactions.
360-MHz clock for high bandwidth.
Two-word burst on all accesses.
Double data rate (DDR) interfaces on both read and write ports (data transferred at 720 MHz) at 360 MHz.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
Echo clocks (CQ and CQ) sim.

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Published: Mar 13, 2017 |