Datasheet4U.com

CY7C1562XV18 - 72-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture

Cypress (now Infineon)

📥 Download Datasheet

CY7C1562XV18 72-mbit qdr ii+ xtreme sram two-word burst architecture by Cypress (now Infineon) - Datasheet Preview

Datasheet Details

Part number	CY7C1562XV18
Manufacturer	Cypress (now Infineon)
File Size	1.20 MB
Description	72-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture
Datasheet	CY7C1562XV18 Datasheet

Overview

CY7C1562XV18/CY7C1564XV18 72-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 72-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.

Key Features

Separate independent read and write data ports.
Supports concurrent transactions.
450 MHz clock for high bandwidth.
Two-word burst for reducing address bus frequency.
Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 900 MHz) at 450 MHz.
Available in 2.5 clock cycle latency.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Echo clocks (CQ and CQ) simplify data capture in high speed syst.

More Datasheets from Cypress (now Infineon)

Part Number	Description
CY7C15632KV18	72-Mbit QDR II+ SRAM Four-Word Burst Architecture
CY7C1563XV18	72-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture
CY7C1564XV18	72-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture
CY7C1565KV18	72-Mbit QDR II+ SRAM Four-Word Burst Architecture
CY7C1565XV18	72-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture
CY7C1568KV18	72-Mbit DDR II+ SRAM Two-Word Burst Architecture
CY7C150	1Kx4 Static RAM
CY7C1510AV18	72-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1510V18	1.8V Synchronous Pipelined SRAM
CY7C1511AV18	72-Mbit QDR-II SRAM 4-Word Burst Architecture