CY7C1550KV18 Overview
CY7C1548KV18/CY7C1550KV18 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency).
CY7C1550KV18 Key Features
- 72-Mbit density (4M × 18, 2M × 36)
- 450-MHz clock for high bandwidth
- 2-word burst for reducing address bus frequency
- Double data rate (DDR) interfaces (data transferred at
- Available in 2.0 clock cycle latency
- Two input clocks (K and K) for precise DDR timing
- SRAM uses rising edges only
- Echo clocks (CQ and CQ) simplify data capture in high-speed
- Data valid pin (QVLD) to indicate valid data on the output
- Synchronous internally self-timed writes