CY7C1550KV18 Datasheet 72-Mbit DDR II+ SRAM Two-Word Burst Architecture

Manufacturer: Cypress (now Infineon)

Overview: CY7C1548KV18/CY7C1550KV18 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.

Download the CY7C1550KV18 datasheet PDF. This datasheet also includes the CY7C1548KV18 variant, as both parts are published together in a single manufacturer document.

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CY7C1550KV18 72-mbit ddr ii+ sram two-word burst architecture by Cypress (now Infineon) - Datasheet Preview

Datasheet Details

Part number	CY7C1550KV18
Manufacturer	Cypress (now Infineon)
File Size	631.46 KB
Description	72-Mbit DDR II+ SRAM Two-Word Burst Architecture
Download	CY7C1550KV18 Download (PDF)

Key Features

72-Mbit density (4M × 18, 2M × 36).
450-MHz clock for high bandwidth.
2-word burst for reducing address bus frequency.
Double data rate (DDR) interfaces (data transferred at 900 MHz) at 450 MHz.
Available in 2.0 clock cycle latency.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Echo clocks (CQ and CQ) simplify data capture in high-speed systems.
Data valid pin (QVLD) to indicate valid data on the output.
Synchro.

More Datasheets from Cypress (now Infineon)

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