CY7C1525V18

Manufacturer: Cypress (now Infineon)

This datasheet includes multiple variants, all published together in a single manufacturer document.

Datasheet Details

Part number	CY7C1525V18
Datasheet	CY7C1525V18 CY7C1510V18 Datasheet (PDF)
File Size	389.43 KB
Manufacturer	Cypress (now Infineon)
Description	1.8V Synchronous Pipelined SRAM

CY7C1510V18, CY7C1525V18 CY7C1512V18, CY7C1514V18 72-Mbit QDR™-II SRAM 2-Word Burst Architecture.

Separate independent read and write data ports
Supports concurrent transactions
250 MHz clock for high bandwidth
2-word burst on all accesses
Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 500 MHz) at 250 MHz
Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
Echo clocks (CQ and CQ) simplify data capture in high-speed systems
Single multiplexed address input bus latches address inputs for both read and write ports

Part Number	Description
CY7C1525AV18	72-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1525KV18	72-Mbit QDR II SRAM Two-Word Burst Architecture
CY7C1520KV18	72-Mbit DDR-II SRAM Two-Word Burst Architecture
CY7C1520V18	1.8V Synchronous Pipelined SRAM
CY7C1521KV18	72-Mbit DDR II SRAM Four-Word Burst Architecture
CY7C1521V18	1.8V Synchronous Pipelined SRAM
CY7C1522AV18	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1522JV18	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1522KV18	72-Mbit DDR II SIO SRAM 2-Word Burst Architecture
CY7C1522V18	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture