CY7C1525KV18 Datasheet

Manufacturer: Cypress (now Infineon)

Datasheet Details

Part number	CY7C1525KV18
Datasheet	CY7C1525KV18-CypressSemiconductor.pdf
File Size	620.47 KB
Manufacturer	Cypress (now Infineon)
Description	72-Mbit QDR II SRAM Two-Word Burst Architecture

CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 72-Mbit QDR® II SRAM Two-Word Burst Architecture 72-Mbit QDR® II SRAM Two-Word Burst.

Separate independent read and write data ports
Supports concurrent transactions
350 MHz clock for high bandwidth
Two-word burst on all accesses
Double data rate (DDR) interfaces on both read and write ports (data transferred at 700 MHz) at 350 MHz
Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
Echo clocks (CQ and CQ) simplify data capture in high speed systems
Single multiplexed address input bus latches address inputs for both read and write ports

Part Number	Description
CY7C1525AV18	72-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1525V18	1.8V Synchronous Pipelined SRAM
CY7C1520KV18	72-Mbit DDR-II SRAM Two-Word Burst Architecture
CY7C1520V18	1.8V Synchronous Pipelined SRAM
CY7C1521KV18	72-Mbit DDR II SRAM Four-Word Burst Architecture
CY7C1521V18	1.8V Synchronous Pipelined SRAM
CY7C1522AV18	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1522JV18	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1522KV18	72-Mbit DDR II SIO SRAM 2-Word Burst Architecture
CY7C1522V18	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture