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CY7C1520V18 Datasheet

Manufacturer: Cypress (now Infineon)

This datasheet includes multiple variants, all published together in a single manufacturer document.

CY7C1520V18 datasheet preview

Datasheet Details

Part number	CY7C1520V18
Datasheet	CY7C1520V18 CY7C1516V18 Datasheet (PDF)
File Size	400.92 KB
Manufacturer	Cypress (now Infineon)
Description	1.8V Synchronous Pipelined SRAM

CY7C1520V18 Overview

CY7C1516V18, CY7C1527V18 CY7C1518V18, CY7C1520V18 72-Mbit DDR-II SRAM 2-Word Burst Architecture.

CY7C1520V18 Key Features

300 MHz clock for high bandwidth
2-word burst for reducing address bus frequency
Double Data Rate (DDR) interfaces
Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize clock
Echo clocks (CQ and CQ) simplify data capture in high-speed
Synchronous internally self-timed writes
1.8V core power supply with HSTL inputs and outputs
Variable drive HSTL output buffers

More Datasheets from Cypress (now Infineon)

See all Cypress (now Infineon) datasheets

Part Number	Description
CY7C1520KV18	72-Mbit DDR-II SRAM Two-Word Burst Architecture
CY7C1521KV18	72-Mbit DDR II SRAM Four-Word Burst Architecture
CY7C1521V18	1.8V Synchronous Pipelined SRAM
CY7C1522AV18	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1522JV18	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1522KV18	72-Mbit DDR II SIO SRAM 2-Word Burst Architecture
CY7C1522V18	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1523AV18	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1523JV18	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1523KV18	72-Mbit DDR II SIO SRAM 2-Word Burst Architecture

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