• Part: CY7C1520KV18
  • Manufacturer: Cypress
  • Size: 604.50 KB
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Cypress datasheets

CY7C1520KV18 Description

CY7C1518KV18 CY7C1520KV18 72-Mbit DDR-II SRAM Two-Word Burst Architecture 72-Mbit DDR-II SRAM Two-Word Burst Architecture.

CY7C1520KV18 Key Features

  • 72-Mbit density (4M × 18, 2M × 36)
  • 333 MHz clock for high bandwidth
  • Two-word burst for reducing address bus frequency
  • Double data rate (DDR) interfaces (data transferred at
  • Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
  • Two input clocks for output data (C and C) to minimize clock
  • Echo clocks (CQ and CQ) simplify data capture in high speed
  • Synchronous internally self-timed writes
  • DDR II operates with 1.5 cycle read latency when DOFF is