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Cypress Semiconductor Electronic Components Datasheet

CY7C1520KV18 Datasheet

72-Mbit DDR-II SRAM Two-Word Burst Architecture

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CY7C1518KV18
CY7C1520KV18
72-Mbit DDR-II SRAM Two-Word
Burst Architecture
72-Mbit DDR-II SRAM Two-Word Burst Architecture
Features
72-Mbit density (4M × 18, 2M × 36)
333 MHz clock for high bandwidth
Two-word burst for reducing address bus frequency
Double data rate (DDR) interfaces (data transferred at
666 MHz) at 333 MHz
Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
Echo clocks (CQ and CQ) simplify data capture in high speed
systems
Synchronous internally self-timed writes
DDR II operates with 1.5 cycle read latency when DOFF is
asserted HIGH
Operates similar to DDR-I device with 1 cycle read latency
when DOFF is asserted LOW
1.8 V core power supply with HSTL inputs and outputs
Variable drive HSTL output buffers
Expanded HSTL output voltage (1.4 V–VDD)
Supports both 1.5 V and 1.8 V IO supply
Available in 165-ball fine pitch ball grid array (FBGA) package
(13 × 15 × 1.4 mm)
Offered in both Pb-free and non Pb-free packages
JTAG 1149.1 compatible Test Access Port
Phase-locked loop (PLL) for accurate data placement
Configurations
CY7C1518KV18 – 4M × 18
CY7C1520KV18 – 2M × 36
Functional Description
The CY7C1518KV18, and CY7C1520KV18 are 1.8 V
synchronous pipelined SRAM equipped with DDR II architecture.
The DDR II consists of an SRAM core with advanced
synchronous peripheral circuitry and a 1-bit burst counter.
Addresses for read and write are latched on alternate rising
edges of the input (K) clock. Write data is registered on the rising
edges of both K and K. Read data is driven on the rising edges
of C and C if provided, or on the rising edge of K and K if C/C are
not provided. On CY7C1518KV18 and CY7C1520KV18, the
burst counter takes in the least significant bit of the external
address and bursts two 18-bit words in the case of
CY7C1518KV18 and two 36-bit words in the case of
CY7C1520KV18 sequentially into or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design. Output data clocks (C/C) enable maximum system
clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
For a complete list of related documentation, click here.
Selection Guide
Maximum Operating Frequency
Maximum Operating Current
Description
× 18
× 36
333 MHz
333
520
640
300 MHz
300
490
600
250 MHz
250
430
530
Unit
MHz
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-00437 Rev. *U
• San Jose, CA 95134-1709 • 408-943-2600
Revised February 4, 2016


Cypress Semiconductor Electronic Components Datasheet

CY7C1520KV18 Datasheet

72-Mbit DDR-II SRAM Two-Word Burst Architecture

No Preview Available !

CY7C1518KV18
CY7C1520KV18
Logic Block Diagram – CY7C1518KV18
Burst
A0 Logic
A(21:0)
22 21
A(21:1)
LD
Address
Register
K
K
DOFF
CLK
Gen.
VREF
R/W
BWS[1:0]
Control
Logic
Write
Reg
Write
Reg
Read Data Reg.
36
18
18
18
Output
Logic
Control
R/W
C
C
Reg.
Reg.
Reg. 18
18
18
CQ
CQ
DQ[17:0]
Logic Block Diagram – CY7C1520KV18
A0
Burst
Logic
A(20:0)
21 20
A(20:1)
LD
Address
Register
K
K
DOFF
CLK
Gen.
VREF
R/W
BWS[3:0]
Control
Logic
Write
Reg
Write
Reg
Read Data Reg.
72
36
36
36
Output
Logic
Control
R/W
C
C
Reg.
Reg.
Reg. 36
36
36
CQ
CQ
DQ[35:0]
Document Number: 001-00437 Rev. *U
Page 2 of 32


Part Number CY7C1520KV18
Description 72-Mbit DDR-II SRAM Two-Word Burst Architecture
Maker Cypress Semiconductor
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CY7C1520KV18 Datasheet PDF






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