Datasheet4U Logo Datasheet4U.com

CY7C1517V18 Datasheet

1.8v Synchronous Pipelined Sram

Manufacturer: Cypress (now Infineon)

CY7C1517V18 Overview

72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36) 300-MHz clock for high bandwidth 4-Word burst for reducing address bus frequency Double Data Rate (DDR) interfaces (data transferred at 600 MHz) @ 300 MHz Two input clocks (K and K) for precise DDR timing.

CY7C1517V18 Key Features

  • 300-MHz clock for high bandwidth
  • 4-Word burst for reducing address bus frequency
  • Double Data Rate (DDR) interfaces
  • Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
  • Two input clocks for output data (C and C) to minimize
  • Synchronous internally self-timed writes
  • 1.8V core power supply with HSTL inputs and outputs
  • Variable drive HSTL output buffers
  • Expanded HSTL output voltage (1.4V-VDD)

More Datasheets from Cypress (now Infineon)

Part Number Description
CY7C1510AV18 72-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1510V18 1.8V Synchronous Pipelined SRAM
CY7C1511AV18 72-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1511JV18 72-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1511KV18 (CY7C15xxKV18) 72-Mbit QDR II SRAM 4-Word Burst Architecture
CY7C1511V18 (CY7C15xxV18) SRAM 4-Word Burst Architecture
CY7C1512 64K x 8 Static RAM
CY7C1512AV18 72-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1512KV18 72-Mbit QDR II SRAM Two-Word Burst Architecture
CY7C1512V18 1.8V Synchronous Pipelined SRAM

CY7C1517V18 Distributor