Description
The CY7C1511V18, CY7C1526V18, CY7C1513V18, and CY7C1515V18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture..
Features
- Separate Independent Read and Write Data Ports.
- Supports concurrent transactions.
- 250-MHz Clock for High Bandwidth.
- 4-Word Burst for reducing address bus frequency.
- Double Data Rate (DDR) interfaces on both Read and Write Ports (data transferred at 500 MHz) at 250 MHz.
- Two input clocks (K and K) for precise DDR timing.
- SRAM uses rising edges only.
- Two output clocks (C and C) accounts for clock skew and flight time mismatchi.
