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CY7C1515V18 Datasheet (CY7C15xxV18) SRAM 4-Word Burst Architecture

Manufacturer: Cypress (now Infineon)

Download the CY7C1515V18 datasheet PDF. This datasheet also includes the CY7C1511V18 variant, as both parts are published together in a single manufacturer document.

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Note: The manufacturer provides a single datasheet file (CY7C1511V18_CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

General Description

The CY7C1511V18, CY7C1526V18, CY7C1513V18, and CY7C1515V18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture.

QDR-II architecture consists of two separate ports to access the memory array.

The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data Inputs to support Write operations.

Overview

www.DataSheet4U.com PRELIMINARY CY7C1511V18 CY7C1526V18 CY7C1513V18 CY7C1515V18 72-Mbit QDR™-II SRAM 4-Word Burst.

Key Features

  • Separate Independent Read and Write Data Ports.
  • Supports concurrent transactions.
  • 250-MHz Clock for High Bandwidth.
  • 4-Word Burst for reducing address bus frequency.
  • Double Data Rate (DDR) interfaces on both Read and Write Ports (data transferred at 500 MHz) at 250 MHz.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Two output clocks (C and C) accounts for clock skew and flight time mismatchi.