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CY7C1512KV18 - 72-Mbit QDR II SRAM Two-Word Burst Architecture

Download the CY7C1512KV18 datasheet PDF. This datasheet also covers the CY7C1525KV18 variant, as both devices belong to the same 72-mbit qdr ii sram two-word burst architecture family and are provided as variant models within a single manufacturer datasheet.

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Note: The manufacturer provides a single datasheet file (CY7C1525KV18-CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

Overview

CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 72-Mbit QDR® II SRAM Two-Word Burst Architecture 72-Mbit QDR® II SRAM Two-Word Burst.

Key Features

  • Separate independent read and write data ports.
  • Supports concurrent transactions.
  • 350 MHz clock for high bandwidth.
  • Two-word burst on all accesses.
  • Double data rate (DDR) interfaces on both read and write ports (data transferred at 700 MHz) at 350 MHz.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
  • Echo clocks (CQ and CQ) sim.

More Datasheets from Cypress (now Infineon)

Part Number Description
CY7C1512 64K x 8 Static RAM
CY7C1512AV18 72-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1512V18 1.8V Synchronous Pipelined SRAM
CY7C1510AV18 72-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1510V18 1.8V Synchronous Pipelined SRAM
CY7C1511AV18 72-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1511JV18 72-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1511KV18 (CY7C15xxKV18) 72-Mbit QDR II SRAM 4-Word Burst Architecture
CY7C1511V18 (CY7C15xxV18) SRAM 4-Word Burst Architecture
CY7C1513AV18 72-Mbit QDR-II SRAM 4-Word Burst Architecture