CY7C1512KV18
Key Features
- Separate independent read and write data ports ❐ Supports concurrent transactions
- 350 MHz clock for high bandwidth
- Two-word burst on all accesses
- Double data rate (DDR) interfaces on both read and write ports (data transferred at 700 MHz) at 350 MHz
- Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only
- Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
- Echo clocks (CQ and CQ) simplify data capture in high speed systems
- Single multiplexed address input bus latches address inputs for both read and write ports
- Separate port selects for depth expansion
- Synchronous internally self-timed writes
