CY7C1510V18 Datasheet

Manufacturer: Cypress (now Infineon)

Datasheet Details

Part number	CY7C1510V18
Datasheet	CY7C1510V18-CypressSemiconductor.pdf
File Size	389.43 KB
Manufacturer	Cypress (now Infineon)
Description	1.8V Synchronous Pipelined SRAM

CY7C1510V18, CY7C1525V18 CY7C1512V18, CY7C1514V18 72-Mbit QDR™-II SRAM 2-Word Burst Architecture.

Separate independent read and write data ports
Supports concurrent transactions
250 MHz clock for high bandwidth
2-word burst on all accesses
Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 500 MHz) at 250 MHz
Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
Echo clocks (CQ and CQ) simplify data capture in high-speed systems
Single multiplexed address input bus latches address inputs for both read and write ports

Part Number	Description
CY7C1510AV18	72-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1511AV18	72-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1511JV18	72-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1511KV18	(CY7C15xxKV18) 72-Mbit QDR II SRAM 4-Word Burst Architecture
CY7C1511V18	(CY7C15xxV18) SRAM 4-Word Burst Architecture
CY7C1512	64K x 8 Static RAM
CY7C1512AV18	72-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1512KV18	72-Mbit QDR II SRAM Two-Word Burst Architecture
CY7C1512V18	1.8V Synchronous Pipelined SRAM
CY7C1513AV18	72-Mbit QDR-II SRAM 4-Word Burst Architecture