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CY7C1510AV18 Datasheet 72-Mbit QDR-II SRAM 2-Word Burst Architecture

Manufacturer: Cypress (now Infineon)

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General Description

Maximum Operating Frequency Maximum Operating Current x8 x9 x18 x36 250 MHz 250 1230 1240 1350 1560 Configurations CY7C1510AV18 – 8M x 8 CY7C1525AV18 – 8M x 9 CY7C1512AV18 – 4M x 18 CY7C1514AV18 – 2M x 36 Functional Description The CY7C1510AV18, CY7C1525AV18, CY7C1512AV18, and CY7C1514AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture.

QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array.

The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support

Overview

CY7C1510AV18, CwYww7.DCat1a5Sh2ee5t4AU.Vco1m8 CY7C1512AV18, CY7C1514AV18 72-Mbit QDR™-II SRAM 2-Word Burst.

Key Features

  • Separate independent read and write data ports.
  • Supports concurrent transactions.
  • 250 MHz clock for high bandwidth.
  • 2-word burst on all accesses.
  • Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 500 MHz) at 250 MHz.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
  • Echo clocks (CQ and CQ) simpl.

More Datasheets from Cypress (now Infineon)

Part Number Description
CY7C1510V18 1.8V Synchronous Pipelined SRAM
CY7C1511AV18 72-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1511JV18 72-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1511KV18 (CY7C15xxKV18) 72-Mbit QDR II SRAM 4-Word Burst Architecture
CY7C1511V18 (CY7C15xxV18) SRAM 4-Word Burst Architecture
CY7C1512 64K x 8 Static RAM
CY7C1512AV18 72-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1512KV18 72-Mbit QDR II SRAM Two-Word Burst Architecture
CY7C1512V18 1.8V Synchronous Pipelined SRAM
CY7C1513AV18 72-Mbit QDR-II SRAM 4-Word Burst Architecture