CY7C1510AV18 Datasheet | Cypress

Features - Separate independent read and write data ports - Supports concurrent transactions - 250 MHz clock for high bandwidth - 2-word burst on all accesses - Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 500 MHz) at 250 MHz - Two input clocks (K and K) for precise DDR timing - SRAM uses rising edges only - Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches - Echo clocks (CQ and CQ) simplify data capture in high-speed systems - Single multiplexed address input bus latches address inputs for both read and write ports - Separate port selects for depth expansion - Synchronous internally self-timed writes - QDR-II operates with 1.5 cycle read latency when Delay Lock Loop (DLL) is enabled - Operates as a QDR-I device with 1 cycle read latency in DLL off mode - Available in x 8, x 9, x 18, and x 36 configurations - Full data coherency, providing most current data - Core VDD = 1.8V (±0.1V); IO VDDQ = 1.4V to VDD - Available in 165-Ball FBGA package (15 x 17 x 1.4 mm) - Offered in both Pb-free and non Pb-free packages - Variable drive HSTL output buffers - JTAG 1149.1 patible test access port - Delay Lock Loop (DLL) for accurate data placement Selection Guide Description Maximum Operating Frequency Maximum Operating Current x8 x9 x18 x36 250 MHz 250 1230 1240 1350 1560 Configurations - 8M x 8 CY7C1525AV18 - 8M x 9 CY7C1512AV18 - 4M x 18 CY7C1514AV18 - 2M x 36 Functional Description The CY7C1510AV18, CY7C1525AV18, CY7C1512AV18, and CY7C1514AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR-II architecture has separate data inputs and data outputs to pletely eliminate the need to...