CY7C150 Datasheet | Cypress

Features - Memory reset function - 1024 x 4 static RAM for control store in high-speed puters - CMOS for optimum speed/power - High speed - 10 ns (mercial) - 12 ns (military) - Low power - 495 m W (mercial) - 550 m W (military) - Separate inputs and outputs - 5-volt power supply ±10% tolerance in both mercial and military - Capable of withstanding greater than 2001V static discharge - TTL-patible inputs and outputs Separate I/O paths eliminates the need to multiplex data in and data out, providing for simpler board layout and faster system performance. Outputs are three-stated during write, reset, deselect, or when output enable (OE) is held HIGH, allowing for easy memory expansion. Reset is initiated by selecting the device (CS = LOW) and taking the reset (RS) input LOW. Within two memory cycles all bits are internally cleared to zero. Since chip select must be LOW for the device to be reset, a global reset signal can be employed, with only selected devices being cleared at any given time. Writing to the device is acplished when the chip select (CS) and write enable (WE) inputs are both LOW. Data on the four data inputs (D0- D3) is written into the memory location specified on the address pins (A0 through A9). Reading the device is acplished by taking chip select (CS) and output enable (OE) LOW while write enable (WE) remains HIGH. Under these conditions, the contents of the memory location specified on the address pins will appear on the four output pins (O0 through O3). The output pins remain in high-impedance state when chip enable (CE) or output enable (OE) is HIGH, or write enable (WE) or reset (RS) is LOW. Functional Description The CY7C150 is a high-performance CMOS static RAM designed for use in cache memory, high-speed graphics, and A die coat is used to insure alpha immunity. data-acquisition applications. The CY7C150 has a memory reset feature that allows the entire memory to be reset in two . memory cycles. Data Shee Logic Block Diagram D0 D1 D2 D3...