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CY7C1486V33 Datasheet (CY7C1480V33 / CY7C1482V33 / CY7C1486V33) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM

Manufacturer: Cypress (now Infineon)

General Description

[1] The CY7C1480V33/CY7C1482V33/CY7C1486V33 SRAM integrates 2,097,152 x 36/4,194,304 x 18,1,048,576 × 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation.

All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK).

The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX, and BWE), and Global Write (GW).

Overview

PRELIMINARY CY7C1480V33 CY7C1482V33 CY7C1486V33 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync.

Key Features

  • Supports bus operation up to 250 MHz.
  • Available speed grades are 250, 200,167 MHz.
  • Registered inputs and outputs for pipelined operation.
  • 3.3V core power supply.
  • 2.5V / 3.3V I/O operation.
  • Fast clock-to-output times.
  • 3.0 ns (for 250-MHz device).
  • 3.0 ns (for 200-MHz device).
  • 3.4 ns (for 167-MHz device).
  • Provide high-performance 3-1-1-1 access rate.
  • User-selectable burst counter supporting Intel® Pe.