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Cypress Semiconductor Electronic Components Datasheet

CY7C1474BV25 Datasheet

(CY7C147xBV25) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM

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CY7C1470BV25
CY7C1472BV25, CY7C1474BV25
72-Mbit (2M x 36/4M x 18/1M x 72)
Pipelined SRAM with NoBL™ Architecture
Features
Pin-compatible and functionally equivalent to ZBT™
Supports 250 MHz bus operations with zero wait states
Available speed grades are 250, 200, and 167 MHz
Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
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Fully registered (inputs and outputs) for pipelined operation
Byte Write capability
Single 2.5V power supply
2.5V IO supply (VDDQ)
Fast clock-to-output times
3.0 ns (for 250-MHz device)
Clock Enable (CEN) pin to suspend operation
Synchronous self-timed writes
CY7C1470BV25, CY7C1472BV25 available in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and
non-Pb-free 165-ball FBGA package. CY7C1474BV25
available in Pb-free and non-Pb-free 209-ball FBGA package
IEEE 1149.1 JTAG Boundary Scan compatible
Burst capability—linear or interleaved burst order
“ZZ” Sleep Mode option and Stop Clock option
Functional Description
The CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25
are 2.5V, 2M x 36/4M x 18/1M x 72 synchronous pipelined burst
SRAMs with No Bus Latency™ (NoBL™) logic, respectively.
They are designed to support unlimited true back-to-back read
or write operations with no wait states. The CY7C1470BV25,
CY7C1472BV25, and CY7C1474BV25 are equipped with the
advanced (NoBL) logic required to enable consecutive read or
write operations with data being transferred on every clock cycle.
This feature dramatically improves the throughput of data in
systems that require frequent read or write transitions. The
CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 are
pin-compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the Clock Enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle. Write operations are controlled by the Byte Write Selects
(BWa–BWd for CY7C1470BV25, BWa–BWb for
CY7C1472BV25, and BWa–BWh for CY7C1474BV25) and a
Write Enable (WE) input. All writes are conducted with on-chip
synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence.
Selection Guide
Description
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
250 MHz
3.0
450
120
200 MHz
3.0
450
120
167 MHz
3.4
400
120
Unit
ns
mA
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-15032 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised February 29, 2008
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Cypress Semiconductor Electronic Components Datasheet

CY7C1474BV25 Datasheet

(CY7C147xBV25) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM

No Preview Available !

CY7C1470BV25
CY7C1472BV25, CY7C1474BV25
Logic Block Diagram – CY7C1470BV25 (2M x 36)
A0, A1, A
MODE
CLK C
CEN
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ADV/LD
BW a
BW b
BW c
BW d
WE
OE
CE1
CE2
CE3
ZZ
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 D1
Q1 A1'
A0 D0 BURST Q0 A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
INPUT
REGISTER 1 E
O
U
T
P
U
T
D
A
T
A
O
U
T
P
U
T
R
E
S
B
G
I
S
T
E
R
S
E
T
E
E
R
I
N
U
F
F
E
R
S
E
G
INPUT
REGISTER 0 E
DQ s
DQ Pa
DQ Pb
DQ Pc
DQ Pd
READ LOGIC
SLEEP
CONTROL
Logic Block Diagram – CY7C1472BV25 (4M x 18)
A0, A1, A
MODE
CLK C
CEN
ADV/LD
BW a
BW b
WE
OE
CE1
CE2
CE3
ZZ
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 D1
Q1 A1'
A0 D0 BURST Q0 A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
O
U
T
S
E
N
P
U
T
MEMORY
ARRAY
S
E
A
M
P
S
R
E
G
I
S
T
E
R
S
E
O
U
T
DP
AU
TT
A
B
SU
TF
EF
EE
RR
IS
N
G
E
INPUT
REGISTER 1 E
INPUT
REGISTER 0 E
DQ s
DQ Pa
DQ Pb
READ LOGIC
Sleep
Control
Document #: 001-15032 Rev. *D
Page 2 of 29
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Part Number CY7C1474BV25
Description (CY7C147xBV25) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM
Maker Cypress Semiconductor
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CY7C1474BV25 Datasheet PDF






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Cypress Semiconductor





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