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Cypress Semiconductor Electronic Components Datasheet

CY7C138 Datasheet

4K x 8/9 Dual-Port Static RAM

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CY7C138 CY7C1394K x 8/9 Dual-Port Static RAM
with Sem, Int, Busy
CY7C138
CY7C139
Features
• True Dual-Ported memory cells that allow simultaneous
reads of the same memory location
• 4K x 8 organization (CY7C138)
• 4K x 9 organization (CY7C139)
• 0.65-micron CMOS for optimum speed/power
• High-speed access: 15 ns
• Low operating power: ICC = 160 mA (max.)
• Fully asynchronous operation
• Automatic power-down
• TTL compatible
• Expandable data bus to 32/36 bits or more using
Master/Slave chip select when using more than one
device
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• INT flag for port-to-port communication
• Available in 68-pin PLCC
• Pb-Free packages available
Functional Description
The CY7C138 and CY7C139 are high-speed CMOS 4K x 8
and 4K x 9 dual-port static RAMs. Various arbitration schemes
Logic BlockDiagram
R/WL
CEL
OEL
4K x 8/9 Dual-Port Static RAM
with Sem, Int, Busy
are included on the CY7C138/9 to handle situations when
multiple processors access the same piece of data. Two ports
are provided permitting independent, asynchronous access
for reads and writes to any location in memory. The
CY7C138/9 can be utilized as a standalone 8/9-bit dual-port
static RAM or multiple devices can be combined in order to
function as a 16/18-bit or wider master/slave dual-port static
RAM. An M/S pin is provided for implementing 16/18-bit or
wider memory applications without the need for separate
master and slave devices or additional discrete logic. Appli-
cation areas include interprocessor/multiprocessor designs,
communications status buffering, and dual-port
video/graphics memory.
Each port has independent control pins: chip enable (CE),
read or write enable (R/W), and output enable (OE). Two flags
are provided on each port (BUSY and INT). BUSY signals that
the port is trying to access the same location currently being
accessed by the other port. The interrupt flag (INT) permits
communication between ports or systems by means of a mail
box. The semaphores are used to pass a flag, or token, from
one port to the other to indicate that a shared resource is in
use. The semaphore logic is comprised of eight shared
latches. Only one side can control the latch (semaphore) at
any time. Control of a semaphore indicates that a shared
resource is in use. An automatic power-down feature is
controlled independently on each port by a chip enable (CE)
pin or SEM pin.
The CY7C138 and CY7C139 are available in a 68-pin PLCC.
R/WR
CER
OER
(7C139)II//OO78LL
I/O0L
BUSYL[1, 2]
A11L
A0L
I/O
CONTROL
I/O
CONTROL
ADDRESS
DECODER
MEMORY
ARRAY
ADDRESS
DECODER
II//OO78RR (7C139)
I/O0R
BUSYR[1, 2]
A11R
A0R
CEL
OEL
R/WL
INSTELM[2L]
Notes:
1. BUSY is an output in master mode and an input in slave mode.
2. Interrupt: push-pull output and requires no pull-up resistor.
INTERRUPT
SEMAPHORE
ARBITRATION
M/S
CER
OER
R/WR
SEMR
INTR[2]
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-06037 Rev. *B
Revised September 6, 2005


Cypress Semiconductor Electronic Components Datasheet

CY7C138 Datasheet

4K x 8/9 Dual-Port Static RAM

No Preview Available !

Pin Configurations
\
68-Pin PLCC
Top View
I/O2L
I/O3L
I/O4L
I/O5L
GND
I/O6L
I/O7L
VCC
GND
I/O0R
I/O1R
I/O2R
VCC
I/O3R
I/O4R
I/O5R
I/O6R
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
10 60
11 59
12 58
13 57
14 56
15 55
16 54
17
CY7C138/9
53
18 52
19 51
20 50
21 49
22 48
23 47
24 46
25 45
26 44
2728 29 30 3132 33 34 35 36 37 38 39 40 41 42 43
A5L
A4L
A3L
A2L
A1L
A0L
INTL
BUSYL
GND
M/S
BUSYR
INTR
A0R
A1R
A2R
A3R
A4R
CY7C138
CY7C139
Pin Definitions
Left Port
I/O0L–7L(8L)
A0L–11L
CEL
OEL
R/WL
SEML
Right Port
I/O0R–7R(8R)
A0R–11R
CER
OER
R/WR
SEMR
INTL
BUSYL
M/S
VCC
GND
INTR
BUSYR
Description
Data Bus Input/Output
Address Lines
Chip Enable
Output Enable
Read/Write Enable
Semaphore Enable. When asserted LOW, allows access to eight
semaphores. The three least significant bits of the address lines will
determine which semaphore to write or read. The I/O0 pin is used when
writing to a semaphore. Semaphores are requested by writing a 0 into the
respective location.
Interrupt Flag. INTL is set when right port writes location FFE and is cleared
when left port reads location FFE. INTR is set when left port writes location
FFF and is cleared when right port reads location FFF.
Busy Flag
Master or Slave Select
Power
Ground
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current
Maximum Standby Current for ISB1
Notes:
3. I/O8R on the CY7C139.
4. I/O8L on the CY7C139.
Commercial
Commercial
7C138-15
7C139-15
15
220
60
7C138-25
7C139-25
25
180
40
7C138-35
7C139-35
35
160
30
7C138-55
7C139-55
55
160
30
Unit
ns
mA
mA
Document #: 38-06037 Rev. *B
Page 2 of 16


Part Number CY7C138
Description 4K x 8/9 Dual-Port Static RAM
Maker Cypress Semiconductor
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CY7C138 Datasheet PDF






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