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Cypress Semiconductor Electronic Components Datasheet

CY7C1372KV25 Datasheet

18-Mbit (512K x 36/1M x 18) Pipelined SRAM

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CY7C1370KV25
CY7C1372KV25
18-Mbit (512K × 36/1M × 18)
Pipelined SRAM with NoBL™ Architecture
18-Mbit (512K × 36/1M × 18) Pipelined SRAM with NoBL™ Architecture
Features
Pin-compatible and functionally equivalent to ZBT™
Supports 200-MHz bus operations with zero wait states
Available speed grades are 200 and 167 MHz
Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
Fully registered (inputs and outputs) for pipelined operation
Byte write capability
Single 2.5 V core power supply (VDD)
2.5 V I/O power supply (VDDQ)
Fast clock-to-output times
3.2 ns (for 200-MHz device)
Clock enable (CEN) pin to suspend operation
Synchronous self-timed writes
Available in JEDEC-standard Pb-free 100-pin TQFP, and non
Pb-free 165-ball FBGA packages
IEEE 1149.1 JTAG-compatible boundary scan
Burst capability – linear or interleaved burst order
“ZZ” sleep mode option and stop clock option
Functional Description
The CY7C1370KV25 and CY7C1372KV25 are 2.5 V, 512K × 36
and 1M × 18 synchronous pipelined burst SRAMs with No Bus
Latency™ (NoBL™) logic, respectively. They are designed to
support unlimited true back-to-back read/write operations with
no wait states. The CY7C1370KV25 and CY7C1372KV25 are
equipped with the advanced NoBL logic required to enable
consecutive read/write operations with data being transferred on
every clock cycle. This feature dramatically improves the
throughput of data in systems that require frequent write/read
transitions. The CY7C1370KV25 and CY7C1372KV25 are
pin-compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle.
Write operations are controlled by the byte write selects
(BWa–BWd for CY7C1370KV25 and BWa–BWb for
CY7C1372KV25) and a write enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
Selection Guide
Maximum access time
Maximum operating current
Description
× 18
× 36
200 MHz
3.0
158
178
167 MHz
3.4
143
163
Unit
ns
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-97851 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 26, 2016


Cypress Semiconductor Electronic Components Datasheet

CY7C1372KV25 Datasheet

18-Mbit (512K x 36/1M x 18) Pipelined SRAM

No Preview Available !

CY7C1370KV25
CY7C1372KV25
Logic Block Diagram – CY7C1370KV25
CLK
CEN
A0, A1, A
MODE
C
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 D1
Q1 A1'
A0 D0 BURST Q0 A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
ADV/LD
BWa
BWb
BWc
BWd
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
INPUT
REGISTER 1 E
O
U
T
P
U
T
D
A
T
A
O
U
T
P
U
T
R
E
S
B
G
I
S
T
E
R
S
E
T
E
E
R
I
N
U
F
F
E
R
S
E
G
INPUT
REGISTER 0 E
OE
CE1
CE2
CE3
ZZ
READ LOGIC
SLEEP
CONTROL
Logic Block Diagram – CY7C1372KV25
A0, A1, A
MODE
CLK C
CEN
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 D1
Q1 A1'
A0 D0 BURST Q0 A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
DQs
DQPa
DQPb
DQPc
DQPd
ADV/LD
BWa
BWb
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
O
U
T
DP
AU
TT
A
B
SU
TF
EF
EE
RR
IS
N
G
E
INPUT
REGISTER 1 E
INPUT
REGISTER 0 E
DQs
DQPa
DQPb
OE
CE1
CE2
CE3
ZZ
READ LOGIC
Sleep
Control
Document Number: 001-97851 Rev. *F
Page 2 of 31


Part Number CY7C1372KV25
Description 18-Mbit (512K x 36/1M x 18) Pipelined SRAM
Maker Cypress Semiconductor
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