CY7C1372B sram equivalent, (cy7c1370b / cy7c1372b) 512k x 36/1m x 18 pipelined sram.
* Zero Bus Latency, no dead cycles between Write and Read cycles
* Fast clock speed: 200, 167, 150, and 133 MHz
* Fast access time: 3.0, 3.4, 3.8, and 4.2 ns .
* Interleaved or linear four-word burst capability
* Individual byte Write (BWSa
–BWSd) control (.
The CY7C1370B and CY7C1372B SRAMs are designed to eliminate dead cycles when transitions from Read to Write or vice versa. These SRAMs are optimized for 100 percent bus utilization and achieve Zero Bus Latency. They integrate 524,288 × 36 and 1,048,5.
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