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Cypress Semiconductor Electronic Components Datasheet

CY7C1372B Datasheet

(CY7C1370B / CY7C1372B) 512K X 36/1M X 18 Pipelined SRAM

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CY7C1370B
CY7C1372B
512K × 36/1M × 18 Pipelined SRAM with NoBLArchitecture
Features
Zero Bus Latency, no dead cycles between Write and
Read cycles
Fast clock speed: 200, 167, 150, and 133 MHz
Fast access time: 3.0, 3.4, 3.8, and 4.2 ns
Internally synchronized registered outputs eliminate
the need to control OE
Single 3.3V 5% and +10% power supply VDD
Separate VDDQ for 3.3V or 2.5V I/O
Single WE (Read/Write) control pin
Positive clock-edge triggered address, data, and
control signal registers for fully pipelined applications
Interleaved or linear four-word burst capability
Individual byte Write (BWSaBWSd) control (may be
tied LOW)
CEN pin to enable clock and suspend operations
Three chip enables for simple depth expansion
JTAG boundary scan (BGA package only)
Available in 119-ball bump BGA and 100-pin TQFP
packages
Automatic power down available using ZZ mode or CE
deselect
Functional Description
The CY7C1370B and CY7C1372B SRAMs are designed to
eliminate dead cycles when transitions from Read to Write or
vice versa. These SRAMs are optimized for 100 percent bus
utilization and achieve Zero Bus Latency. They integrate
524,288 × 36 and 1,048,576 × 18 SRAM cells, respectively,
with advanced synchronous peripheral circuitry and a 2-bit
counter for internal burst operation. The Synchronous Burst
SRAM family employs high-speed, low-power CMOS designs
www.DautsaiSngheeatd4Uva.cnocmed single-layer polysilicon, three-layer metal
technology. Each memory cell consists of six transistors.
All synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock input (CLK). The synchronous
inputs include all addresses, all data inputs, depth-expansion
Chip Enables (CE1, CE2, and CE3), cycle start input (ADV/LD),
Clock enable (CEN), byte Write Enables (BWSa, BWSb,
BWSc, and BWSd), and Read-Write Control (WE). BWSc and
BWSd apply to CY7C1370B only.
Address and control signals are applied to the SRAM during
one clock cycle, and two cycles later, its associated data
occurs, either Read or Write.
A Clock enable (CEN) pin allows operation of the
CY7C1370B/CY7C1372B to be suspended as long as
necessary. All synchronous inputs are ignored when CEN is
HIGH and the internal device registers will hold their previous
values.
There are three chip enable pins (CE1, CE2, CE3) that allow
the user to deselect the device when desired. If any one of
these three are not active when ADV/LD is LOW, no new
memory operation can be initiated and any burst cycle in
progress is stopped. However, any pending data transfers
(Read or Write) will be completed. The data bus will be in
high-impedance state two cycles after the chip is deselected
or a Write cycle is initiated.
The CY7C1370B and CY7C1372B have an on-chip two-bit
burst counter. In the burst mode, the CY7C1370B and
CY7C1372B provide four cycles of data for a single address
presented to the SRAM. The order of the burst sequence is
defined by the MODE input pin. The MODE pin selects
between linear and interleaved burst sequence. The ADV/LD
signal is used to load a new external address (ADV/LD = LOW)
or increment the internal burst counter (ADV/LD = HIGH)
Output enable (OE) and burst sequence select (MODE) are
the asynchronous signals. OE can be used to disable the
outputs at any given time. ZZ may be tied to LOW if it is not
used.
Four pins are used to implement JTAG test capabilities. The
JTAG circuitry is used to serially shift data to and from the
device. JTAG inputs use LVTTL/LVCMOS levels to shift data
during this testing mode of operation.
Logic Block Diagram
CLK
CE
DaDta-In
Q
REG.
ADV/LD
Ax
CY7C1370 CY7C1372
AX X = 18:0
X = 19:0
DQX X = a, b, c, d X = a, b
DPX X = a, b, c, d X = a, b
BWSX X = a, b, c, d X = a, b
CEN
CE1
CE2
CE3
WE
BWSX
Mode
OE
CONTROL
and Write
LOGIC
256K × 36/
512K × 18
MEMORY
ARRAY
DQX
DPX
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05197 Rev. **
Revised December 3, 2001


Cypress Semiconductor Electronic Components Datasheet

CY7C1372B Datasheet

(CY7C1370B / CY7C1372B) 512K X 36/1M X 18 Pipelined SRAM

No Preview Available !

.
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Pin Configurations
Commercial
200 MHz
3.0
315
20
167MHz
3.4
285
20
100-Pin TQFP Packages
150 MHz
3.8
265
20
CY7C1370B
CY7C1372B
133 MHz
4.2
245
20
Unit
ns
mA
mA
DPc 1
DQc 2
DQc
VDDQ
3
4
VSS
DQc
5
6
DQc 7
DQc 8
DQc
VSS
VDDQ
9
10
11
DQc 12
DQc
NC
VDD
NC
VSS
DQd
13
14
15
16
17
18
DQd 19
VDDQ 20
VSS 21
DQd 22
DQd 23
DQd 24
www.DaDtaQSdheet245U.com
VSS 26
VDDQ 27
DQd 28
DQd 29
DPd 30
CY7C1370B
(512K × 36)
80 DPb
NC 1
79 DQb NC 2
78 DQb NC 3
77 VDDQ VDDQ 4
76 VSS
VSS 5
75 DQb NC 6
74 DQb NC 7
73 DQb DQb 8
72 DQb DQb 9
71
70
VSS
VSS
VDDQ VDDQ
10
11
69 DQb DQb 12
68 DQb DQb 13
67 VSS
NC 14
66 NC
VDD
15
65 VDD
NC
16
64 ZZ
VSS
17
63 DQa DQb 18
62 DQa DQb 19
61 VDDQ VDDQ 20
60 VSS
VSS
21
59 DQa DQb 22
58 DQa DQb 23
57 DQa DPb 24
56 DQa NC 25
55 VSS
VSS 26
54 VDDQ VDDQ 27
53 DQa NC 28
52 DQa NC 29
51 DPa NC 30
CY7C1372B
(1M × 18)
80 A
79 NC
78 NC
77 VDDQ
76 VSS
75 NC
74 DPa
73 DQa
72 DQa
71 VSS
70 VDDQ
69 DQa
68 DQa
67 VSS
66 NC
65 VDD
64 ZZ
63 DQa
62 DQa
61 VDDQ
60 VSS
59 DQa
58 DQa
57 NC
56 NC
55 VSS
54 VDDQ
53 NC
52 NC
51 NC
Document #: 38-05197 Rev. **
Page 2 of 27


Part Number CY7C1372B
Description (CY7C1370B / CY7C1372B) 512K X 36/1M X 18 Pipelined SRAM
Maker Cypress Semiconductor
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CY7C1372B Datasheet PDF






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