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CY7C1372B - (CY7C1370B / CY7C1372B) 512K X 36/1M X 18 Pipelined SRAM

Download the CY7C1372B datasheet PDF. This datasheet also covers the CY7C1370B variant, as both devices belong to the same (cy7c1370b / cy7c1372b) 512k x 36/1m x 18 pipelined sram family and are provided as variant models within a single manufacturer datasheet.

Description

The CY7C1370B and CY7C1372B SRAMs are designed to eliminate dead cycles when transitions from Read to Write or vice versa.

These SRAMs are optimized for 100 percent bus utilization and achieve Zero Bus Latency.

Features

  • Zero Bus Latency, no dead cycles between Write and Read cycles.
  • Fast clock speed: 200, 167, 150, and 133 MHz.
  • Fast access time: 3.0, 3.4, 3.8, and 4.2 ns.
  • Internally synchronized registered outputs eliminate the need to control OE.
  • Single 3.3V.
  • 5% and +10% power supply VDD.
  • Separate VDDQ for 3.3V or 2.5V I/O.
  • Single WE (Read/Write) control pin.
  • Positive clock-edge triggered address, data, and control signal register.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1370B_CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
CY7C1372C 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture Cypress
CY7C1372CV25 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture Cypress
CY7C1372D 18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM Cypress
CY7C1370C 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture Cypress
CY7C1370CV25 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture Cypress

Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C1372DV25 18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1372KV25 18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1372KV33 18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1372KVE33 18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1370B (CY7C1370B / CY7C1372B) 512K X 36/1M X 18 Pipelined SRAM

Full PDF Text Transcription

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CY7C1370B CY7C1372B 512K × 36/1M × 18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between Write and Read cycles • Fast clock speed: 200, 167, 150, and 133 MHz • Fast access time: 3.0, 3.4, 3.8, and 4.2 ns • Internally synchronized registered outputs eliminate the need to control OE • Single 3.3V –5% and +10% power supply VDD • Separate VDDQ for 3.3V or 2.
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