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Cypress Semiconductor Electronic Components Datasheet

CY7C1367C Datasheet

9-Mbit Pipelined DCD Sync SRAM

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CY7C1366C
CY7C1367C
9-Mbit (256K × 36/512K × 18)
Pipelined DCD Sync SRAM
9-Mbit (256K × 36/512K × 18) Pipelined DCD Sync SRAM
Features
Supports bus operation up to 166 MHz
Available speed grade is 166 MHz
Registered inputs and outputs for pipelined operation
Optimal for performance (double-cycle deselect)
• Depth expansion without wait state
3.3 V – 5% and + 10% core power supply (VDD)
2.5 V/3.3 V I/O power supply (VDDQ)
Fast clock-to-output times
3.5 ns (for 166 MHz device)
Provide high performance 3-1-1-1 access rate
User-selectable burst counter supporting IntelPentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous output enable
Available in Pb-free 100-pin TQFP and non Pb-free 119-ball
BGA package
IEEE 1149.1 JTAG-compatible boundary scan
“ZZ” sleep mode option
Functional Description
The CY7C1366C/CY7C1367C SRAM integrates 256K × 36 and
512K × 18 SRAM cells with advanced synchronous peripheral
circuitry and a two-bit counter for internal burst operation. All
synchronous inputs are gated by registers controlled by a
positive-edge-triggered clock input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelining
CchEip3[1e])n, abbulerst(CcEon1)t,rodl einppthu-tesxp(AanDsSioCn,
chip enables (CE2 and
ADSP, and ADV), write
enables (BWX, and BWE), and global write (GW). Asynchronous
inputs include the output enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed write cycle.This part supports byte write
operations (see Pin Definitions on page 6 and Partial Truth Table
for Read/Write on page 9 for further details). Write cycles can be
one to four bytes wide as controlled by the byte write control
inputs. GW active LOW causes all bytes to be written. This
device incorporates an additional pipelined enable register which
delays turning off the output buffers an additional cycle when a
deselect is executed. This feature enables depth expansion
without penalizing system performance.
The CY7C1366C/CY7C1367C operates from a +3.3 V core
power supply while all outputs operate with a +3.3 V or a +2.5 V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
For a complete list of related documentation, click here.
Selection Guide
Maximum access time
Maximum operating current
Maximum CMOS standby current
Description
166 MHz
3.5
180
40
Unit
ns
mA
mA
Note
1. CE3 is for 100-pin TQFP. 119-ball BGA is offered only in 2 Chip Enable.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05542 Rev. *M
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 9, 2016


Cypress Semiconductor Electronic Components Datasheet

CY7C1367C Datasheet

9-Mbit Pipelined DCD Sync SRAM

No Preview Available !

CY7C1366C
CY7C1367C
Logic Block Diagram – CY7C1366C
A 0,A1,A
MODE
ADV
CLK
ADSC
ADSP
BW D
BW C
BW B
BW A
BWE
GW
CE 1
CE 2
CE 3
OE
ZZ
ADDRESS
REGISTER
2 A[1:0]
BURST Q1
COUNTER AND
LOGIC
CLR Q0
DQ D,DQP D
BYTE
WRITE REGISTER
DQ c,DQP C
BYTE
WRITE REGISTER
DQ B,DQP B
BYTE
WRITE REGISTER
DQ A, DQP A
BYTE
WRITE REGISTER
ENABLE
REGISTER
PIPELINED
ENABLE
DQ D,DQP D
BYTE
WRITE DRIVER
DQ c,DQP C
BYTE
WRITE DRIVER
DQ B,DQP B
BYTE
WRITE DRIVER
DQ A, DQP A
BYTE
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs
DQP A
DQP B
DQP C
DQP D
INPUT
REGISTERS
SLEEP
CONTROL
Logic Block Diagram – CY7C1367C
A 0, A1, A
MODE
ADV
CLK
ADSC
ADSP
BW B
BW A
BWE
GW
CE 1
CE 2
CE 3
OE
ZZ
ADDRESS
REGISTER
2 A[1:0]
Q1
BURST
COUNTER AND
LOGIC
CLR Q0
DQ B, DQP B
BYTE
WRITE REGISTER
DQ A , DQP A
BYTE
WRITE REGISTER
ENABLE
REGISTER
PIPELINED
ENABLE
SLEEP
CONTROL
DQ B , DQP B
BYTE
WRITE DRIVER
DQ A, DQP A
BYTE
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQ s,
DQP A
DQP B
INPUT
REGISTERS
Document Number: 38-05542 Rev. *M
Page 2 of 31


Part Number CY7C1367C
Description 9-Mbit Pipelined DCD Sync SRAM
Maker Cypress Semiconductor
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